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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id p25sm468118ood.4.2021.06.01.13.10.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Jun 2021 13:10:28 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [PATCH v3 0/4] Add Rockchip SFC(serial flash controller) support Date: Tue, 1 Jun 2021 15:10:17 -0500 Message-Id: <20210601201021.4406-1-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Chris Morgan I'm trying to revive an abandoned patch series for the Rockchip serial flash controller (SFC) found on the Rockchip PX30 SOC, as well as other SOCs by Rockchip. I'm picking this up from version 8 of the patch series located from here: http://patchwork.ozlabs.org/project/linux-mtd/cover/1518091958-3672-1-git-send-email-andy.yan@rock-chips.com/ Changes made in v3: - Changed the name of the clocks to sfc/ahb (from clk-sfc/clk-hsfc). - Changed the compatible string from rockchip,sfc to rockchip,rk3036-sfc. A quick glance at the datasheets suggests this driver should work for the PX30, RK180x, RK3036, RK312x, RK3308 and RV1108 SoCs, and possibly more. However, I am currently only able to test this on a PX30 (an RK3326). The technical reference manuals appear to list the same registers for each device. - Corrected devicetree documentation for formatting and to note these changes. - Replaced the maintainer with Heiko Stuebner and myself, as we will take ownership of this going forward. - Noted that the device (per the reference manual) supports 4 CS, but I am only able to test a single CS (CS 0). - Reordered patches to comply with upstream rules. Changes made in v2: - Reimplemented driver using spi-mem subsystem. - Removed power management code as I couldn't get it working properly. - Added device tree bindings for Odroid Go Advance. Changes made in this new series versus the v8 of the old series: - Added function to read spi-rx-bus-width from device tree, in the event that the SPI chip supports 4x mode but only has 2 pins wired (such as the Odroid Go Advance). - Changed device tree documentation from txt to yaml format. - Made "reset" message a dev_dbg from a dev_info. - Changed read and write fifo functions to remove redundant checks. - Changed the write and read from relaxed to non-relaxed when starting the DMA transfer or reading the DMA IRQ. - Changed from dma_coerce_mask_and_coherent to just dma_set_mask_and_coherent. - Changed name of get_if_type to rockchip_sfc_get_if_type. Chris Morgan (4): dt-bindings: rockchip-sfc: Bindings for Rockchip serial flash controller spi: rockchip-sfc: add rockchip serial flash controller driver arm64: dts: rockchip: Add SFC to PX30 arm64: dts: rockchip: Enable SFC for Odroid Go Advance .../devicetree/bindings/spi/rockchip,sfc.yaml | 87 ++ arch/arm64/boot/dts/rockchip/px30.dtsi | 38 + .../boot/dts/rockchip/rk3326-odroid-go2.dts | 16 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-rockchip-sfc.c | 861 ++++++++++++++++++ 6 files changed, 1012 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/rockchip,sfc.yaml create mode 100644 drivers/spi/spi-rockchip-sfc.c