From patchwork Fri Aug 5 05:30:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naga Sureshkumar Relli X-Patchwork-Id: 12936850 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6D74C00140 for ; Fri, 5 Aug 2022 05:30:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231181AbiHEFay (ORCPT ); Fri, 5 Aug 2022 01:30:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230448AbiHEFax (ORCPT ); Fri, 5 Aug 2022 01:30:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1BF219034; Thu, 4 Aug 2022 22:30:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1659677452; x=1691213452; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=ybjdxYxYvszXJlnk/4cZ/S6YHu9uFWE1YAwhkjvIe1k=; b=PwtXw500Fe0rmB6aycFLV5t+4qbY62WdCKvs9lEsfEaJj6QuFnxQSxwt gHfGdRu+OtxI90jvwwq4edStC2QgrJMbhvpdB3z/NMGyhl727eBStQk55 Qw6LePB1QlJWu7e//BZ7g9pbn4JfE0zqSdKoST/M+3j+BxAsHvSiGvxZc 5ZfPcoPqofQ51C/G3n1BLx8GQk065EgRI3gK+xwhsscGMl00UAaL1EB6x NHT85Lge1qMqrOnF6LOkI9QPsxjULwum72YGqHb+e9q5Z0YSom+iX73Zl 22i0IKQx85yoX39v/8t/QC4JdPDhFptCzncjQ1vm7idVEQMnm+IC7OPsL w==; X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="175187468" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 04 Aug 2022 22:30:52 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 4 Aug 2022 22:30:51 -0700 Received: from microchip-OptiPlex-5040.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Thu, 4 Aug 2022 22:30:48 -0700 From: Naga Sureshkumar Relli To: , , , CC: , , , , Naga Sureshkumar Relli Subject: [PATCH v3 0/4] Add support for Microchip QSPI controller Date: Fri, 5 Aug 2022 11:00:15 +0530 Message-ID: <20220805053019.996484-1-nagasuresh.relli@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI controller support. Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI. changes in v3 ------------ 1. Added dev_err_probe() at places like probe failures 2. Split the dt-bindings one for adding coreqspi compatible and other one to add coreqspi as fallback to mpfs-qspi. changes in v2 ------------ 1. Replaced spi_alloc_master() with devm_spi_alloc_master() 2. Used dev_err_probe() when devm_spi_alloc_master() fails. 3. Added shared IRQ flag in the interrupt registration. 4. Updated the dt_bindings so that there is a differentiation between FPGA QSPI IP core and hard QSPI IP core. Naga Sureshkumar Relli (4): spi: dt-binding: document microchip coreQSPI spi: dt-binding: add coreqspi as a fallback for mpfs-qspi spi: microchip-core-qspi: Add support for microchip fpga qspi controllers MAINTAINERS: add qspi to Polarfire SoC entry .../bindings/spi/microchip,mpfs-spi.yaml | 15 +- MAINTAINERS | 1 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-microchip-core-qspi.c | 601 ++++++++++++++++++ 5 files changed, 623 insertions(+), 4 deletions(-) create mode 100644 drivers/spi/spi-microchip-core-qspi.c Reviewed-by: Conor Dooley