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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2023 13:01:59.3973 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3815865c-84c7-4399-7702-08db05e6d617 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4068 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Tegra234 and Tegra241 chips have QSPI controller that supports TCG PC Client Specific TPM Interface Specification (TIS) flow control. Since the controller only supports half duplex, sw wait polling (flow control using full duplex transfers) method implemented in tpm_tis_spi_main.c does not suffice. Added extended driver to disable sw flow control and send all transfers in single message. Flow control is handled by hardware. V2: Fix dt schema errors. Krishna Yarlagadda (4): dt-bindings: tpm: Add compatible for Tegra TPM tpm: tegra: Support SPI tpm wait state detect spi: dt-bindings: Add Tegra TPM wait polling flag spi: tegra210-quad: Enable TPM wait polling .../security/tpm/nvidia,tegra-tpm-spi.yaml | 34 +++++ ...nvidia,tegra210-quad-peripheral-props.yaml | 6 + drivers/char/tpm/Makefile | 1 + drivers/char/tpm/tpm_tis_spi.h | 1 + drivers/char/tpm/tpm_tis_spi_main.c | 4 +- drivers/char/tpm/tpm_tis_spi_tegra.c | 123 ++++++++++++++++++ drivers/spi/spi-tegra210-quad.c | 16 +++ 7 files changed, 184 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/security/tpm/nvidia,tegra-tpm-spi.yaml create mode 100644 drivers/char/tpm/tpm_tis_spi_tegra.c