| Message ID | 20240529074037.1345882-1-wsadowski@marvell.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Marvell HW overlay support for Cadence xSPI | expand |
On Wed, 29 May 2024 00:40:31 -0700, Witold Sadowski wrote: > This patch series adds support for the second version of the Marvell > hardware overlay for the Cadence xSPI IP block. The overlay is a hardware > change made around the original xSPI block. It extends xSPI features with > clock configuration, interrupt masking, and full-duplex, variable-length SPI > operations. > > These functionalities allow the xSPI block to operate not only with memory > devices but also with simple SPI devices and TPM devices. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/5] spi: cadence: Ensure data lines set to low during dummy-cycle period commit: 4a69c1264ff41bc5bf7c03101ada0454fbf08868 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
This patch series adds support for the second version of the Marvell hardware overlay for the Cadence xSPI IP block. The overlay is a hardware change made around the original xSPI block. It extends xSPI features with clock configuration, interrupt masking, and full-duplex, variable-length SPI operations. These functionalities allow the xSPI block to operate not only with memory devices but also with simple SPI devices and TPM devices. Changes: v6: Fix item order in cdns,xspi.yaml v5: Rework cdns,xspi.yaml file Reword commit messages Move mamory mapping to ACPI patch Use devm_platform_ioremap_resource instead of two step mapping v4: Rename new Marvell registers to keep naming conventions Rename mrvl,xspi-nor to marvell,cnxx,xspi-nor Various fixed for cdns,xspi.yaml file: - Remove unnecesary parameters - Link register xferbase with marvell,cn10-xspi-nor - Move default values to .c file from device-tree Clock configuration optimization ACPI fixes: - Remove incorrect ACPI match table Added .data field to device_id, fixes for matching in ACPI and dtb case Minor style comment changes v3: Removed all kconfig changes Added device-tree mrvl,xspi-nor tag v2: Support for second overlay iteration v1: - v0: Initial support for v1 overlay Piyush Malgujar (1): spi: cadence: Allow to read basic xSPI configuration from ACPI Witold Sadowski (4): spi: cadence: Ensure data lines set to low during dummy-cycle period spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI spi: cadence: Add Marvell xSPI IP overlay changes spi: cadence: Add MRVL overlay xfer operation support .../devicetree/bindings/spi/cdns,xspi.yaml | 32 +- drivers/spi/spi-cadence-xspi.c | 620 +++++++++++++++++- 2 files changed, 628 insertions(+), 24 deletions(-)