From patchwork Wed May 29 07:40:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Witold Sadowski X-Patchwork-Id: 13677976 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B542E16936B; Wed, 29 May 2024 07:40:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.156.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716968448; cv=none; b=cdmW3md7fbxvYbwlWzkHB/tgm78zS+ZoJqD2kBvZfN/a4iUx+vLydtHHYAYTE5JLH9xyTirg6pavNTw88qqRcAQDaswUEx9G6+kkN/EZaiuXYn3Hhai8mVFnEsKAVUeEhXOEemlK9tc2eok9ffes/tOsvnEDJZmjzODjsl3VXmI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716968448; c=relaxed/simple; bh=kSilMQSfl+5MyGEDzYOr+qcVPR4ct4u+aq7Z1++L2nE=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=gruQovlIR/P4AaWR5rvVZRaysQDL8pcqkQEZgKZposve3pbiZczuKIDeHcjKxhFB5aYWUoSd7FF+fr/uNanrmB/YK4YxTh/FAMaPJdlnJ6g5sXPnYN0vrcieRrKnywUsiw+T7qZDABIqf30WQ3py5p6I+EVJk9Er5xIlYkEUthE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=JKGvHeCf; arc=none smtp.client-ip=67.231.156.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="JKGvHeCf" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 44T3mGtP007681; Wed, 29 May 2024 00:40:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:message-id :mime-version:subject:to; s=pfpt0220; bh=PTuQk/inFajXWQGCYw++v9j uwG87FCwyYjwbktM2DU4=; b=JKGvHeCfKF3CQPRwg5/DwVTWYLPfhllECGHJkT2 dcOJl9qu2irkP9KU1tmLozRreKXbhhYoM0qsdbwpuUhZa/yP5J5l/grVLuoi2VfU Fd4f7R6RQLuAetrXtN+30yQJsGabKva7+MB31mvSUwx4BtKs/N7fj0u7n3JFcaPQ 1KzcbwFiPAmasLTg55d7QgZG95jte2p8L7l8gDAjNMlWo0vzwRqlvJz5riIHg+Q3 zYuG1YW6LLMQeqT0Ewt3kqatEY7/aKGB0DJJyQoOZGORH75ZOA2F57B6SzJLWmWB d7GITfb88JW2gP7CUZLeHWnGjw5uZ9aLLc9rmcZR1cnGJPg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3yddnvc79e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 May 2024 00:40:41 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 29 May 2024 00:40:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 29 May 2024 00:40:40 -0700 Received: from Dell2s-9.sclab.marvell.com (unknown [10.110.150.250]) by maili.marvell.com (Postfix) with ESMTP id 2A3B23F7051; Wed, 29 May 2024 00:40:40 -0700 (PDT) From: Witold Sadowski To: , , CC: , , , , , Witold Sadowski Subject: [PATCH v6 0/5] Marvell HW overlay support for Cadence xSPI Date: Wed, 29 May 2024 00:40:31 -0700 Message-ID: <20240529074037.1345882-1-wsadowski@marvell.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: K44NXRiiVw347ssCbLm3lmCH6-vpKDft X-Proofpoint-ORIG-GUID: K44NXRiiVw347ssCbLm3lmCH6-vpKDft X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-28_14,2024-05-28_01,2024-05-17_01 This patch series adds support for the second version of the Marvell hardware overlay for the Cadence xSPI IP block. The overlay is a hardware change made around the original xSPI block. It extends xSPI features with clock configuration, interrupt masking, and full-duplex, variable-length SPI operations. These functionalities allow the xSPI block to operate not only with memory devices but also with simple SPI devices and TPM devices. Changes: v6: Fix item order in cdns,xspi.yaml v5: Rework cdns,xspi.yaml file Reword commit messages Move mamory mapping to ACPI patch Use devm_platform_ioremap_resource instead of two step mapping v4: Rename new Marvell registers to keep naming conventions Rename mrvl,xspi-nor to marvell,cnxx,xspi-nor Various fixed for cdns,xspi.yaml file: - Remove unnecesary parameters - Link register xferbase with marvell,cn10-xspi-nor - Move default values to .c file from device-tree Clock configuration optimization ACPI fixes: - Remove incorrect ACPI match table Added .data field to device_id, fixes for matching in ACPI and dtb case Minor style comment changes v3: Removed all kconfig changes Added device-tree mrvl,xspi-nor tag v2: Support for second overlay iteration v1: - v0: Initial support for v1 overlay Piyush Malgujar (1): spi: cadence: Allow to read basic xSPI configuration from ACPI Witold Sadowski (4): spi: cadence: Ensure data lines set to low during dummy-cycle period spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI spi: cadence: Add Marvell xSPI IP overlay changes spi: cadence: Add MRVL overlay xfer operation support .../devicetree/bindings/spi/cdns,xspi.yaml | 32 +- drivers/spi/spi-cadence-xspi.c | 620 +++++++++++++++++- 2 files changed, 628 insertions(+), 24 deletions(-)