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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD82.mail.protection.outlook.com (10.167.244.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Wed, 18 Sep 2024 10:52:18 +0000 Received: from airavat.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 18 Sep 2024 05:51:18 -0500 From: Raju Rangoju To: , CC: , , , , Subject: [PATCH 0/9] spi: spi_amd: Performance Optimization Patch Series Date: Wed, 18 Sep 2024 16:20:28 +0530 Message-ID: <20240918105037.406003-1-Raju.Rangoju@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD82:EE_|CH3PR12MB9342:EE_ X-MS-Office365-Filtering-Correlation-Id: 93663559-ec8a-464c-cf58-08dcd7cff728 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2024 10:52:18.3835 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93663559-ec8a-464c-cf58-08dcd7cff728 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD82.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9342 AMD SPI controller’s index mode performance is constrained by the hardware limitation of the FIFO queue length. This patch series introduces optimizations to the spi_amd driver, aiming to maximize throughput and enhance overall performance. The changes includes, - Enabling SPI dual and quad I/O modes - Optimize I/O operations using efficient kernel APIs - Optimize I/O operations by optimizing set tx/rx count functions - Optimize I/O operations by reducing the data read calls to fetch the data from FIFO queues - Add changes to support AMD HID2 SPI controller - Add changes to enhance SPI-MEM support functions to reflect hardware capabilities - Add changes to set SPI controller address mode before initiating the commands - Add changes to implement HIDDMA read operation support for HID2 SPI controller Raju Rangoju (9): spi: spi_amd: Sort headers alphabetically spi: spi_amd: Enable dual and quad I/O modes spi: spi_amd: Replace ioread/iowrite calls spi: spi_amd: Updates to set tx/rx count functions spi: spi_amd: Optimize IO operations spi: spi_amd: Add support for HID2 SPI controller spi: spi_amd: Enhance SPI-MEM support functions spi: spi_amd: Set controller address mode spi: spi_amd: Add HIDDMA basic read support drivers/spi/spi-amd.c | 325 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 295 insertions(+), 30 deletions(-)