| Message ID | 20241113-imx-spi-word-delay-v2-0-2b65b737bf29@pengutronix.de (mailing list archive) |
|---|---|
| Headers | show |
| Series | spi: imx: support word delay in ecspi | expand |
On Wed, 13 Nov 2024 13:18:30 +0100, Jonas Rebmann wrote: > The i.MX SPI controller supports inserting a configurable delay between > subsequent words, which is needed for some slower devices that couldn't > keep up otherwise. > > This patch series introduces support for the word delay parameters for > i.MX51 onwards. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/2] spi: imx: pass struct spi_transfer to prepare_transfer() commit: 7b94af24a7a4d12a76183f1b2f0d363d2c9ced43 [2/2] spi: imx: support word delay commit: a3bb4e663df318b232746478e7b191bcf6e3af40 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
The i.MX SPI controller supports inserting a configurable delay between subsequent words, which is needed for some slower devices that couldn't keep up otherwise. This patch series introduces support for the word delay parameters for i.MX51 onwards. The SPI clock (CSRC=0) was chosen as the clock source over the also available 32.768 KHz Low-Frequency Reference Clock (CSRC=1). The sample period control bits (SAMPLE_PERIOD) are set to the selected word delay converted to SPI clock cycles. A deviation from the requested number of wait cycles and the actual word delay was observed via both software timings and oscilloscope measurements and accounted for. The Chip Select Delay Control bits in the Sample Period Control Register remain zero. Behaviour on i.MX35 and earlier, where the CSPI interface is used, remains unchanged. Signed-off-by: Jonas Rebmann <jre@pengutronix.de> --- Changes in v2: - Remove accidentally added CCs - spi-imx.c: Add missing includes, Rb kernel test robot - Link to v1: https://lore.kernel.org/r/20241107-imx-spi-word-delay-v1-0-2a969214d796@pengutronix.de --- Jonas Rebmann (2): spi: imx: pass struct spi_transfer to prepare_transfer() spi: imx: support word delay drivers/spi/spi-imx.c | 108 ++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 92 insertions(+), 16 deletions(-) --- base-commit: 9852d85ec9d492ebef56dc5f229416c925758edc change-id: 20241009-imx-spi-word-delay-21dc01f098cc Best regards,