[v1,0/2] spi: s3c64xx: add support for samsung,exynos990-spi

Message

Denzeel Oliva Feb. 12, 2025, 7:12 p.m. UTC

The Exynos990 SPI controller shares similarities with
the GS101 (Google Tensor) SPI implementation,
but introduces specific hardware requirements such as
32-bit register access and variable FIFO depths depending on
the SPI node where it will have to be specified in DT (Device Tree).

Denzeel Oliva (2):
  spi: dt-bindings: samsung: add samsung,exynos990-spi compatible
  spi: s3c64xx: add support exynos990-spi to new port config data

 .../devicetree/bindings/spi/samsung,spi.yaml    |  1 +
 drivers/spi/spi-s3c64xx.c                       | 17 +++++++++++++++++
 2 files changed, 18 insertions(+)

Comments

Tudor Ambarus Feb. 13, 2025, 7:05 a.m. UTC | #1

Hi!

On 2/12/25 7:12 PM, Denzeel Oliva wrote:
> The Exynos990 SPI controller shares similarities with
> the GS101 (Google Tensor) SPI implementation,
> but introduces specific hardware requirements such as
> 32-bit register access and variable FIFO depths depending on

gs101 mandates 32-bit accesses too.

> the SPI node where it will have to be specified in DT (Device Tree).

gs101 has some USI nodes that can work only in uart mode and indeed the
fifosize there is 256. Does downstream define SPI nodes with 256 bytes
FIFOs? Can you please point me the the downstream code?

Cheers,
ta

> 
> Denzeel Oliva (2):
>   spi: dt-bindings: samsung: add samsung,exynos990-spi compatible
>   spi: s3c64xx: add support exynos990-spi to new port config data
> 
>  .../devicetree/bindings/spi/samsung,spi.yaml    |  1 +
>  drivers/spi/spi-s3c64xx.c                       | 17 +++++++++++++++++
>  2 files changed, 18 insertions(+)
>

Denzeel Oliva Feb. 13, 2025, 7:47 p.m. UTC | #2

On Thu, Feb 13, 2025 at 07:05:22AM +0000, Tudor Ambarus wrote:
> gs101 mandates 32-bit accesses too.

Also in exynos990 [0]

> > the SPI node where it will have to be specified in DT (Device Tree).
> 
> gs101 has some USI nodes that can work only in uart mode and indeed the
> fifosize there is 256. Does downstream define SPI nodes with 256 bytes
> FIFOs? Can you please point me the the downstream code?
> 

Yes, Exynos990 has SPI nodes with 256-byte FIFOs, and you can see this in
the downstream kernel. Here are some relevant references:

- SPI8: [1]
- SPI9: [2]
- SPI10: [3]

Best regards,
Denzeel

[0] https://github.com/pascua28/android_kernel_samsung_s20fe/blob/3be539e9cd22b89ba3cc8282945a0c46ff27341d/drivers/spi/spi-s3c64xx.c#L767
[1] https://github.com/pascua28/android_kernel_samsung_s20fe/blob/3be539e9cd22b89ba3cc8282945a0c46ff27341d/arch/arm64/boot/dts/exynos/exynos9830-usi.dtsi#L1641
[2] https://github.com/pascua28/android_kernel_samsung_s20fe/blob/3be539e9cd22b89ba3cc8282945a0c46ff27341d/arch/arm64/boot/dts/exynos/exynos9830-usi.dtsi#L1662
[3] https://github.com/pascua28/android_kernel_samsung_s20fe/blob/3be539e9cd22b89ba3cc8282945a0c46ff27341d/arch/arm64/boot/dts/exynos/exynos9830-usi.dtsi#L1683

Tudor Ambarus Feb. 14, 2025, 6:14 a.m. UTC | #3

On 2/13/25 7:47 PM, Denzeel Oliva wrote:
> Yes, Exynos990 has SPI nodes with 256-byte FIFOs, and you can see this in
> the downstream kernel. Here are some relevant references:

thanks for the references!