From patchwork Wed Nov 17 10:43:41 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sekhar Nori X-Patchwork-Id: 332171 Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oAHB2Cgd016292 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 17 Nov 2010 11:02:33 GMT Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1PIfmG-0002Cw-Jp; Wed, 17 Nov 2010 11:02:12 +0000 Received: from sog-mx-3.v43.ch3.sourceforge.com ([172.29.43.193] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.69) (envelope-from ) id 1PIfmF-0002Cp-Mw for spi-devel-general@lists.sourceforge.net; Wed, 17 Nov 2010 11:02:11 +0000 Received-SPF: pass (sog-mx-3.v43.ch3.sourceforge.com: domain of india.ti.com designates 192.94.94.40 as permitted sender) client-ip=192.94.94.40; envelope-from=a0875516@india.ti.com; helo=arroyo.ext.ti.com; Received: from arroyo.ext.ti.com ([192.94.94.40]) by sog-mx-3.v43.ch3.sourceforge.com with esmtps (TLSv1:AES256-SHA:256) (Exim 4.69) id 1PIfmE-0001uE-TB; Wed, 17 Nov 2010 11:02:11 +0000 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id oAHAiVWq031539 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 17 Nov 2010 04:44:34 -0600 Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id oAHAiQ47021839; Wed, 17 Nov 2010 16:14:26 +0530 (IST) Received: from psplinux051.india.ti.com (localhost [127.0.0.1]) by psplinux051.india.ti.com (8.13.1/8.13.1) with ESMTP id oAHAiNa0030338; Wed, 17 Nov 2010 16:14:23 +0530 Received: (from a0875516@localhost) by psplinux051.india.ti.com (8.13.1/8.13.1/Submit) id oAHAiNaG030335; Wed, 17 Nov 2010 16:14:23 +0530 From: Sekhar Nori To: spi-devel-general@lists.sourceforge.net Subject: [PATCH 09/49] spi: davinci: enable GPIO lines to be used as chip selects Date: Wed, 17 Nov 2010 16:13:41 +0530 Message-Id: <1289990661-30126-10-git-send-email-nsekhar@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: <1289990661-30126-9-git-send-email-nsekhar@ti.com> References: <1289990661-30126-1-git-send-email-nsekhar@ti.com> <1289990661-30126-2-git-send-email-nsekhar@ti.com> <1289990661-30126-3-git-send-email-nsekhar@ti.com> <1289990661-30126-4-git-send-email-nsekhar@ti.com> <1289990661-30126-5-git-send-email-nsekhar@ti.com> <1289990661-30126-6-git-send-email-nsekhar@ti.com> <1289990661-30126-7-git-send-email-nsekhar@ti.com> <1289990661-30126-8-git-send-email-nsekhar@ti.com> <1289990661-30126-9-git-send-email-nsekhar@ti.com> X-Spam-Score: -1.4 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record 0.1 AWL AWL: From: address is in the auto white-list X-Headers-End: 1PIfmE-0001uE-TB Cc: davinci-linux-open-source@linux.davincidsp.com, David Brownell , Sekhar Nori X-BeenThere: spi-devel-general@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux SPI core/device drivers discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: spi-devel-general-bounces@lists.sourceforge.net X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Wed, 17 Nov 2010 11:02:33 +0000 (UTC) diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h index 2cb326e..734d1fb 100644 --- a/arch/arm/mach-davinci/include/mach/spi.h +++ b/arch/arm/mach-davinci/include/mach/spi.h @@ -19,6 +19,8 @@ #ifndef __ARCH_ARM_DAVINCI_SPI_H #define __ARCH_ARM_DAVINCI_SPI_H +#define SPI_INTERN_CS 0xFF + enum { SPI_VERSION_1, /* For DM355/DM365/DM6467 */ SPI_VERSION_2, /* For DA8xx */ @@ -38,6 +40,7 @@ struct davinci_spi_platform_data { u8 use_dma; u8 c2tdelay; u8 t2cdelay; + u8 *chip_sel; }; #endif /* __ARCH_ARM_DAVINCI_SPI_H */ diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 82dddf8..d5d7014 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -238,20 +238,32 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value) struct davinci_spi_platform_data *pdata; u8 chip_sel = spi->chip_select; u16 spidat1_cfg = CS_DEFAULT; + bool gpio_chipsel = false; davinci_spi = spi_master_get_devdata(spi->master); pdata = davinci_spi->pdata; + if (pdata->chip_sel && chip_sel < pdata->num_chipselect && + pdata->chip_sel[chip_sel] != SPI_INTERN_CS) + gpio_chipsel = true; + /* * Board specific chip select logic decides the polarity and cs * line for the controller */ - if (value == BITBANG_CS_ACTIVE) { - spidat1_cfg |= SPIDAT1_CSHOLD_MASK; - spidat1_cfg &= ~(0x1 << chip_sel); - } + if (gpio_chipsel) { + if (value == BITBANG_CS_ACTIVE) + gpio_set_value(pdata->chip_sel[chip_sel], 0); + else + gpio_set_value(pdata->chip_sel[chip_sel], 1); + } else { + if (value == BITBANG_CS_ACTIVE) { + spidat1_cfg |= SPIDAT1_CSHOLD_MASK; + spidat1_cfg &= ~(0x1 << chip_sel); + } - iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); + iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); + } } /** @@ -546,6 +558,7 @@ static void davinci_spi_cleanup(struct spi_device *spi) static int davinci_spi_bufs_prep(struct spi_device *spi, struct davinci_spi *davinci_spi) { + struct davinci_spi_platform_data *pdata; int op_mode = 0; /* @@ -558,8 +571,12 @@ static int davinci_spi_bufs_prep(struct spi_device *spi, op_mode = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; - if (!(spi->mode & SPI_NO_CS)) - op_mode |= 1 << spi->chip_select; + if (!(spi->mode & SPI_NO_CS)) { + pdata = davinci_spi->pdata; + if (!pdata->chip_sel || + pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS) + op_mode |= 1 << spi->chip_select; + } if (spi->mode & SPI_READY) op_mode |= SPIPC0_SPIENA_MASK; @@ -1101,6 +1118,14 @@ static int davinci_spi_probe(struct platform_device *pdev) udelay(100); iowrite32(1, davinci_spi->base + SPIGCR0); + /* initialize chip selects */ + if (pdata->chip_sel) { + for (i = 0; i < pdata->num_chipselect; i++) { + if (pdata->chip_sel[i] != SPI_INTERN_CS) + gpio_direction_output(pdata->chip_sel[i], 1); + } + } + /* Clock internal */ if (davinci_spi->pdata->clk_internal) set_io_bits(davinci_spi->base + SPIGCR1,