@@ -412,7 +412,6 @@ static struct resource dm355_spi0_resources[] = {
static struct davinci_spi_platform_data dm355_spi0_pdata = {
.version = SPI_VERSION_1,
.num_chipselect = 2,
- .clk_internal = 1,
.cshold_bug = true,
};
static struct platform_device dm355_spi0_device = {
@@ -625,7 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
static struct davinci_spi_platform_data dm365_spi0_pdata = {
.version = SPI_VERSION_1,
.num_chipselect = 2,
- .clk_internal = 1,
};
static struct resource dm365_spi0_resources[] = {
@@ -29,7 +29,6 @@ enum {
struct davinci_spi_platform_data {
u8 version;
u8 num_chipselect;
- u8 clk_internal;
u8 intr_line;
u8 *chip_sel;
bool cshold_bug;
@@ -927,14 +927,6 @@ static int davinci_spi_probe(struct platform_device *pdev)
}
}
- /* Clock internal */
- if (davinci_spi->pdata->clk_internal)
- set_io_bits(davinci_spi->base + SPIGCR1,
- SPIGCR1_CLKMOD_MASK);
- else
- clear_io_bits(davinci_spi->base + SPIGCR1,
- SPIGCR1_CLKMOD_MASK);
-
if (pdata->intr_line)
iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
else
@@ -943,6 +935,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF);
/* master mode default */
+ set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
ret = spi_bitbang_start(&davinci_spi->bitbang);