diff mbox

[07/11] spi-dw: Set number of available chip selects correctly

Message ID 1308794413-11069-8-git-send-email-dirk.brandewie@gmail.com
State Superseded, archived
Headers show

Commit Message

dirk.brandewie@gmail.com June 23, 2011, 2 a.m. UTC
From: Dirk Brandewie <dirk.brandewie@gmail.com>

Only four chip selects are available directly off the pins of the
master.

Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
---
 drivers/spi/spi-dw-mid.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

Comments

Grant Likely June 23, 2011, 3:53 a.m. UTC | #1
On Wed, Jun 22, 2011 at 8:00 PM,  <dirk.brandewie@gmail.com> wrote:
> From: Dirk Brandewie <dirk.brandewie@gmail.com>
>
> Only four chip selects are available directly off the pins of the
> master.
>
> Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
> ---
>  drivers/spi/spi-dw-mid.c |    4 +++-
>  1 files changed, 3 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
> index 78e64d3..1d11268 100644
> --- a/drivers/spi/spi-dw-mid.c
> +++ b/drivers/spi/spi-dw-mid.c
> @@ -211,7 +211,9 @@ int spi_dw_mid_init(struct spi_dw *dws)
>        dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
>        iounmap(clk_reg);
>
> -       dws->num_cs = 16;
> +       dws->num_cs = 4;        /* spi_dw_chip_sel() bits 0-3 are
> +                                * valid in the slave enable register
> +                                */

I thought someone had told me that the dw spio core supported using
the 4 cs lines in a multiplex mode to create up to 15 cs lines, but I
may be misremembering.

g.

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diff mbox

Patch

diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 78e64d3..1d11268 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -211,7 +211,9 @@  int spi_dw_mid_init(struct spi_dw *dws)
 	dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 	iounmap(clk_reg);
 
-	dws->num_cs = 16;
+	dws->num_cs = 4;        /* spi_dw_chip_sel() bits 0-3 are
+				 * valid in the slave enable register
+				 */
 	dws->fifo_len = 40;	/* FIFO has 40 words buffer */
 
 #ifdef CONFIG_SPI_DW_MID_DMA