From patchwork Tue Jul 10 13:38:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 1177631 Return-Path: X-Original-To: patchwork-spi-devel-general@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by patchwork1.kernel.org (Postfix) with ESMTP id 4916C40B37 for ; Tue, 10 Jul 2012 13:45:10 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1SoakX-0007on-7p; Tue, 10 Jul 2012 13:45:09 +0000 Received: from sog-mx-2.v43.ch3.sourceforge.com ([172.29.43.192] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1SoakW-0007oh-0z for spi-devel-general@lists.sourceforge.net; Tue, 10 Jul 2012 13:45:08 +0000 Received-SPF: pass (sog-mx-2.v43.ch3.sourceforge.com: domain of nvidia.com designates 216.228.121.35 as permitted sender) client-ip=216.228.121.35; envelope-from=ldewangan@nvidia.com; helo=hqemgate04.nvidia.com; Received: from hqemgate04.nvidia.com ([216.228.121.35]) by sog-mx-2.v43.ch3.sourceforge.com with esmtps (TLSv1:AES256-SHA:256) (Exim 4.76) id 1SoakQ-0004SD-CT for spi-devel-general@lists.sourceforge.net; Tue, 10 Jul 2012 13:45:07 +0000 Received: from hqnvupgp06.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Tue, 10 Jul 2012 06:44:12 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp06.nvidia.com (PGP Universal service); Tue, 10 Jul 2012 06:44:56 -0700 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Tue, 10 Jul 2012 06:44:56 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.264.0; Tue, 10 Jul 2012 06:44:56 -0700 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Tue, 10 Jul 2012 06:44:56 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q6ADipq7000385; Tue, 10 Jul 2012 06:44:52 -0700 (PDT) From: Laxman Dewangan To: , Subject: [PATCH RESEND] spi: tegra: use dmaengine based dma driver Date: Tue, 10 Jul 2012 19:08:37 +0530 Message-ID: <1341927517-4584-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 MIME-Version: 1.0 X-Spam-Score: -1.1 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record 0.4 AWL AWL: From: address is in the auto white-list X-Headers-End: 1SoakQ-0004SD-CT Cc: Laxman, swarren@wwwdotorg.org, linux-kernel@vger.kernel.org, Dewangan , linux-tegra@vger.kernel.org, spi-devel-general@lists.sourceforge.net X-BeenThere: spi-devel-general@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux SPI core/device drivers discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces@lists.sourceforge.net Use the dmaengine based Tegra APB DMA driver for data transfer between SPI FIFO and memory in place of legacy Tegra APB DMA. The new driver is selected if legacy driver is not selected and new DMA driver is enabled through config file. Signed-off-by: Laxman Dewangan Acked-by: Stephen Warren --- As per mail from Grant's, he is moving and Mark B is picking up spi changes, resending this patch. Thanks Mark. Adding ack of Stephen which he has already ack on original patch before his vacation. drivers/spi/Kconfig | 2 +- drivers/spi/spi-tegra.c | 89 ++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 85 insertions(+), 6 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8c8c680..b7b99e7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -366,7 +366,7 @@ config SPI_STMP3XXX config SPI_TEGRA tristate "Nvidia Tegra SPI controller" - depends on ARCH_TEGRA && TEGRA_SYSTEM_DMA + depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA) help SPI driver for NVidia Tegra SoCs diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c index 7f99ff3..ef52c1c 100644 --- a/drivers/spi/spi-tegra.c +++ b/drivers/spi/spi-tegra.c @@ -30,6 +30,7 @@ #include #include +#include #include @@ -162,12 +163,23 @@ struct spi_tegra_data { * require transfers to be 4 byte aligned we need a bounce buffer * for the generic case. */ + int dma_req_len; +#if defined(CONFIG_TEGRA_SYSTEM_DMA) struct tegra_dma_req rx_dma_req; struct tegra_dma_channel *rx_dma; +#else + struct dma_chan *rx_dma; + struct dma_slave_config sconfig; + struct dma_async_tx_descriptor *rx_dma_desc; + dma_cookie_t rx_cookie; +#endif u32 *rx_bb; dma_addr_t rx_bb_phys; }; +#if !defined(CONFIG_TEGRA_SYSTEM_DMA) +static void tegra_spi_rx_dma_complete(void *args); +#endif static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi, unsigned long reg) @@ -190,10 +202,24 @@ static void spi_tegra_go(struct spi_tegra_data *tspi) val = spi_tegra_readl(tspi, SLINK_DMA_CTL); val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN; - val |= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1); + val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1); spi_tegra_writel(tspi, val, SLINK_DMA_CTL); - +#if defined(CONFIG_TEGRA_SYSTEM_DMA) + tspi->rx_dma_req.size = tspi->dma_req_len; tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req); +#else + tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma, + tspi->rx_bb_phys, tspi->dma_req_len, + DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); + if (!tspi->rx_dma_desc) { + dev_err(&tspi->pdev->dev, "dmaengine slave prep failed\n"); + return; + } + tspi->rx_dma_desc->callback = tegra_spi_rx_dma_complete; + tspi->rx_dma_desc->callback_param = tspi; + tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc); + dma_async_issue_pending(tspi->rx_dma); +#endif val |= SLINK_DMA_EN; spi_tegra_writel(tspi, val, SLINK_DMA_CTL); @@ -221,7 +247,7 @@ static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi, spi_tegra_writel(tspi, val, SLINK_TX_FIFO); } - tspi->rx_dma_req.size = len / tspi->cur_bytes_per_word * 4; + tspi->dma_req_len = len / tspi->cur_bytes_per_word * 4; return len; } @@ -318,9 +344,8 @@ static void spi_tegra_start_message(struct spi_device *spi, spi_tegra_start_transfer(spi, t); } -static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req) +static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi) { - struct spi_tegra_data *tspi = req->dev; unsigned long flags; struct spi_message *m; struct spi_device *spi; @@ -380,6 +405,19 @@ static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req) spin_unlock_irqrestore(&tspi->lock, flags); } +#if defined(CONFIG_TEGRA_SYSTEM_DMA) +static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req) +{ + struct spi_tegra_data *tspi = req->dev; + handle_spi_rx_dma_complete(tspi); +} +#else +static void tegra_spi_rx_dma_complete(void *args) +{ + struct spi_tegra_data *tspi = args; + handle_spi_rx_dma_complete(tspi); +} +#endif static int spi_tegra_setup(struct spi_device *spi) { @@ -471,6 +509,9 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev) struct spi_tegra_data *tspi; struct resource *r; int ret; +#if !defined(CONFIG_TEGRA_SYSTEM_DMA) + dma_cap_mask_t mask; +#endif master = spi_alloc_master(&pdev->dev, sizeof *tspi); if (master == NULL) { @@ -522,12 +563,24 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev) INIT_LIST_HEAD(&tspi->queue); +#if defined(CONFIG_TEGRA_SYSTEM_DMA) tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT); if (!tspi->rx_dma) { dev_err(&pdev->dev, "can not allocate rx dma channel\n"); ret = -ENODEV; goto err3; } +#else + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + tspi->rx_dma = dma_request_channel(mask, NULL, NULL); + if (!tspi->rx_dma) { + dev_err(&pdev->dev, "can not allocate rx dma channel\n"); + ret = -ENODEV; + goto err3; + } + +#endif tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN, &tspi->rx_bb_phys, GFP_KERNEL); @@ -537,6 +590,7 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev) goto err4; } +#if defined(CONFIG_TEGRA_SYSTEM_DMA) tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete; tspi->rx_dma_req.to_memory = 1; tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys; @@ -546,6 +600,23 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev) tspi->rx_dma_req.source_wrap = 4; tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id]; tspi->rx_dma_req.dev = tspi; +#else + /* Dmaengine Dma slave config */ + tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; + tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO; + tspi->sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + tspi->sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + tspi->sconfig.slave_id = spi_tegra_req_sels[pdev->id]; + tspi->sconfig.src_maxburst = 1; + tspi->sconfig.dst_maxburst = 1; + ret = dmaengine_device_control(tspi->rx_dma, + DMA_SLAVE_CONFIG, (unsigned long) &tspi->sconfig); + if (ret < 0) { + dev_err(&pdev->dev, "can not do slave configure for dma %d\n", + ret); + goto err4; + } +#endif master->dev.of_node = pdev->dev.of_node; ret = spi_register_master(master); @@ -559,7 +630,11 @@ err5: dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN, tspi->rx_bb, tspi->rx_bb_phys); err4: +#if defined(CONFIG_TEGRA_SYSTEM_DMA) tegra_dma_free_channel(tspi->rx_dma); +#else + dma_release_channel(tspi->rx_dma); +#endif err3: clk_put(tspi->clk); err2: @@ -581,7 +656,11 @@ static int __devexit spi_tegra_remove(struct platform_device *pdev) tspi = spi_master_get_devdata(master); spi_unregister_master(master); +#if defined(CONFIG_TEGRA_SYSTEM_DMA) tegra_dma_free_channel(tspi->rx_dma); +#else + dma_release_channel(tspi->rx_dma); +#endif dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN, tspi->rx_bb, tspi->rx_bb_phys);