From patchwork Thu Aug 16 14:13:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 1332871 Return-Path: X-Original-To: patchwork-spi-devel-general@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) by patchwork2.kernel.org (Postfix) with ESMTP id 1E61BDFB34 for ; Thu, 16 Aug 2012 14:31:31 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=sfs-ml-4.v29.ch3.sourceforge.com) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1T216g-0001xw-Re; Thu, 16 Aug 2012 14:31:30 +0000 Received: from sog-mx-1.v43.ch3.sourceforge.com ([172.29.43.191] helo=mx.sourceforge.net) by sfs-ml-4.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1T216e-0001xa-Vx for spi-devel-general@lists.sourceforge.net; Thu, 16 Aug 2012 14:31:28 +0000 Received-SPF: pass (sog-mx-1.v43.ch3.sourceforge.com: domain of nvidia.com designates 216.228.121.35 as permitted sender) client-ip=216.228.121.35; envelope-from=ldewangan@nvidia.com; helo=hqemgate04.nvidia.com; Received: from hqemgate04.nvidia.com ([216.228.121.35]) by sog-mx-1.v43.ch3.sourceforge.com with esmtps (TLSv1:AES256-SHA:256) (Exim 4.76) id 1T216Z-00045Z-64 for spi-devel-general@lists.sourceforge.net; Thu, 16 Aug 2012 14:31:28 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Thu, 16 Aug 2012 07:30:37 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 16 Aug 2012 07:25:43 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 16 Aug 2012 07:25:43 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.264.0; Thu, 16 Aug 2012 07:31:16 -0700 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Thu, 16 Aug 2012 07:31:16 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q7GEUwhf000972; Thu, 16 Aug 2012 07:31:13 -0700 (PDT) From: Laxman Dewangan To: , , , , Subject: [PATCH 3/5] ARM: tegra: apbio: remove support of legacy DMA driver based access Date: Thu, 16 Aug 2012 19:43:15 +0530 Message-ID: <1345126397-28864-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1345126397-28864-1-git-send-email-ldewangan@nvidia.com> References: <1345126397-28864-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 X-Spam-Score: -1.1 (-) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. -1.5 SPF_CHECK_PASS SPF reports sender host as permitted sender for sender-domain -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain 0.4 AWL AWL: From: address is in the auto white-list X-Headers-End: 1T216Z-00045Z-64 Cc: vinod.koul@linux.intel.com, linux@arm.linux.org.uk, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, Laxman Dewangan , linux-tegra@vger.kernel.org, spi-devel-general@lists.sourceforge.net X-BeenThere: spi-devel-general@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux SPI core/device drivers discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces@lists.sourceforge.net Remove the support code which uses the legacy APB DMA driver for accessing the apbio register. The driver will use the dmaengine based APB DMA driver for accessing apbio register. Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/apbio.c | 118 +------------------------------------------ 1 files changed, 1 insertions(+), 117 deletions(-) diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index 643a378..b5015d0 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c @@ -28,7 +28,7 @@ #include "apbio.h" -#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA) +#if defined(CONFIG_TEGRA20_APB_DMA) static DEFINE_MUTEX(tegra_apb_dma_lock); static u32 *tegra_apb_bb; static dma_addr_t tegra_apb_bb_phys; @@ -37,121 +37,6 @@ static DECLARE_COMPLETION(tegra_apb_wait); static u32 tegra_apb_readl_direct(unsigned long offset); static void tegra_apb_writel_direct(u32 value, unsigned long offset); -#if defined(CONFIG_TEGRA_SYSTEM_DMA) -static struct tegra_dma_channel *tegra_apb_dma; - -bool tegra_apb_init(void) -{ - struct tegra_dma_channel *ch; - - mutex_lock(&tegra_apb_dma_lock); - - /* Check to see if we raced to setup */ - if (tegra_apb_dma) - goto out; - - ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT | - TEGRA_DMA_SHARED); - - if (!ch) - goto out_fail; - - tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32), - &tegra_apb_bb_phys, GFP_KERNEL); - if (!tegra_apb_bb) { - pr_err("%s: can not allocate bounce buffer\n", __func__); - tegra_dma_free_channel(ch); - goto out_fail; - } - - tegra_apb_dma = ch; -out: - mutex_unlock(&tegra_apb_dma_lock); - return true; - -out_fail: - mutex_unlock(&tegra_apb_dma_lock); - return false; -} - -static void apb_dma_complete(struct tegra_dma_req *req) -{ - complete(&tegra_apb_wait); -} - -static u32 tegra_apb_readl_using_dma(unsigned long offset) -{ - struct tegra_dma_req req; - int ret; - - if (!tegra_apb_dma && !tegra_apb_init()) - return tegra_apb_readl_direct(offset); - - mutex_lock(&tegra_apb_dma_lock); - req.complete = apb_dma_complete; - req.to_memory = 1; - req.dest_addr = tegra_apb_bb_phys; - req.dest_bus_width = 32; - req.dest_wrap = 1; - req.source_addr = offset; - req.source_bus_width = 32; - req.source_wrap = 4; - req.req_sel = TEGRA_DMA_REQ_SEL_CNTR; - req.size = 4; - - INIT_COMPLETION(tegra_apb_wait); - - tegra_dma_enqueue_req(tegra_apb_dma, &req); - - ret = wait_for_completion_timeout(&tegra_apb_wait, - msecs_to_jiffies(50)); - - if (WARN(ret == 0, "apb read dma timed out")) { - tegra_dma_dequeue_req(tegra_apb_dma, &req); - *(u32 *)tegra_apb_bb = 0; - } - - mutex_unlock(&tegra_apb_dma_lock); - return *((u32 *)tegra_apb_bb); -} - -static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) -{ - struct tegra_dma_req req; - int ret; - - if (!tegra_apb_dma && !tegra_apb_init()) { - tegra_apb_writel_direct(value, offset); - return; - } - - mutex_lock(&tegra_apb_dma_lock); - *((u32 *)tegra_apb_bb) = value; - req.complete = apb_dma_complete; - req.to_memory = 0; - req.dest_addr = offset; - req.dest_wrap = 4; - req.dest_bus_width = 32; - req.source_addr = tegra_apb_bb_phys; - req.source_bus_width = 32; - req.source_wrap = 1; - req.req_sel = TEGRA_DMA_REQ_SEL_CNTR; - req.size = 4; - - INIT_COMPLETION(tegra_apb_wait); - - tegra_dma_enqueue_req(tegra_apb_dma, &req); - - ret = wait_for_completion_timeout(&tegra_apb_wait, - msecs_to_jiffies(50)); - - if (WARN(ret == 0, "apb write dma timed out")) - tegra_dma_dequeue_req(tegra_apb_dma, &req); - - mutex_unlock(&tegra_apb_dma_lock); -} - -#else static struct dma_chan *tegra_apb_dma_chan; static struct dma_slave_config dma_sconfig; @@ -279,7 +164,6 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) pr_err("error in writing offset 0x%08lx using dma\n", offset); mutex_unlock(&tegra_apb_dma_lock); } -#endif #else #define tegra_apb_readl_using_dma tegra_apb_readl_direct #define tegra_apb_writel_using_dma tegra_apb_writel_direct