From patchwork Fri Mar 21 05:24:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Axel Lin X-Patchwork-Id: 3871221 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 938869F334 for ; Fri, 21 Mar 2014 05:24:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CC2572025A for ; Fri, 21 Mar 2014 05:24:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C2F672025B for ; Fri, 21 Mar 2014 05:24:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752119AbaCUFYX (ORCPT ); Fri, 21 Mar 2014 01:24:23 -0400 Received: from mail-pd0-f173.google.com ([209.85.192.173]:55117 "EHLO mail-pd0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751498AbaCUFYW (ORCPT ); Fri, 21 Mar 2014 01:24:22 -0400 Received: by mail-pd0-f173.google.com with SMTP id z10so1889173pdj.32 for ; Thu, 20 Mar 2014 22:24:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:message-id:subject:from:to:cc:date:content-type :mime-version:content-transfer-encoding; bh=Ht96SiT/n33Wmh1LrELuWDK8brcCxI+b5XknHznzDVg=; b=IOkqyqFs9Ugl0a95uUDhLbc+CtJZbE2S/3PtgsBCqd7t2SbmsGdj/Ca6Raw8Se8vO1 LEiSHOSC2ebEtJEKEST3cv7Eevl2TpQNAm8s/9d02sXb1N9H1ewRjPLQHDvXJG1FW3eB z1IQSA8MmHxt4s1E06wg3rzRqLVwgcGAB8CDRCwhziqBebnWpvPhRyEpqjAB7srKhdez nh7kOI/50UV7eyJNPEeCjcBDnjOwcbzJxF73IMKP1K7Tl9WQI7puZr43RRqv6uMjn2mV SVhfWMOKF4i2fUQScir5GuVOfKjUnuhfnT7AbuQQ5zjyvbXhJiSQIPBcHOuXxze8cIb0 TpwQ== X-Gm-Message-State: ALoCoQkOHh2s0vwPF5/2fbPbiPqh1BUFTD1S1n9xfOnM49GPEh+/ewTtKnBjWYar44bnfTezHC6a X-Received: by 10.66.65.204 with SMTP id z12mr51734439pas.60.1395379462098; Thu, 20 Mar 2014 22:24:22 -0700 (PDT) Received: from [192.168.0.102] (218-164-139-5.dynamic.hinet.net. [218.164.139.5]) by mx.google.com with ESMTPSA id xi5sm20257689pab.27.2014.03.20.22.24.19 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 20 Mar 2014 22:24:21 -0700 (PDT) Message-ID: <1395379454.30136.2.camel@phoenix> Subject: [PATCH] spi: nuc900: Fix setting multiple bits settings in register From: Axel Lin To: Mark Brown Cc: Wan ZongShun , linux-spi@vger.kernel.org Date: Fri, 21 Mar 2014 13:24:14 +0800 X-Mailer: Evolution 3.8.4-0ubuntu1 Mime-Version: 1.0 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The correct way to set multiple bits settings is always clear these bit fields before set new settings. Current code does not cause problem because the reset value of these bit fields are 0, and these settings only set once during probe. Signed-off-by: Axel Lin --- drivers/spi/spi-nuc900.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-nuc900.c b/drivers/spi/spi-nuc900.c index 675c210..16e30de 100644 --- a/drivers/spi/spi-nuc900.c +++ b/drivers/spi/spi-nuc900.c @@ -37,7 +37,9 @@ /* usi register bit */ #define ENINT (0x01 << 17) #define ENFLG (0x01 << 16) +#define SLEEP (0x0f << 12) #define TXNUM (0x03 << 8) +#define TXBITLEN (0x1f << 3) #define TXNEG (0x01 << 2) #define RXNEG (0x01 << 1) #define LSB (0x01 << 10) @@ -115,19 +117,16 @@ static void nuc900_spi_chipsel(struct spi_device *spi, int value) } } -static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, - unsigned int txnum) +static void nuc900_spi_setup_txnum(struct nuc900_spi *hw, unsigned int txnum) { unsigned int val; unsigned long flags; spin_lock_irqsave(&hw->lock, flags); - val = __raw_readl(hw->regs + USI_CNT); + val = __raw_readl(hw->regs + USI_CNT) & ~TXNUM; - if (!txnum) - val &= ~TXNUM; - else + if (txnum) val |= txnum << 0x08; __raw_writel(val, hw->regs + USI_CNT); @@ -144,7 +143,7 @@ static void nuc900_spi_setup_txbitlen(struct nuc900_spi *hw, spin_lock_irqsave(&hw->lock, flags); - val = __raw_readl(hw->regs + USI_CNT); + val = __raw_readl(hw->regs + USI_CNT) & ~TXBITLEN; val |= (txbitlen << 0x03); @@ -283,12 +282,11 @@ static void nuc900_set_sleep(struct nuc900_spi *hw, unsigned int sleep) spin_lock_irqsave(&hw->lock, flags); - val = __raw_readl(hw->regs + USI_CNT); + val = __raw_readl(hw->regs + USI_CNT) & ~SLEEP; if (sleep) val |= (sleep << 12); - else - val &= ~(0x0f << 12); + __raw_writel(val, hw->regs + USI_CNT); spin_unlock_irqrestore(&hw->lock, flags);