From patchwork Thu Apr 17 16:26:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chew Chiau Ee X-Patchwork-Id: 4006321 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4DE3B9F2CC for ; Thu, 17 Apr 2014 08:23:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2287E2012E for ; Thu, 17 Apr 2014 08:23:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C68CC200FE for ; Thu, 17 Apr 2014 08:23:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756459AbaDQIXW (ORCPT ); Thu, 17 Apr 2014 04:23:22 -0400 Received: from mga01.intel.com ([192.55.52.88]:64313 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753207AbaDQIXU (ORCPT ); Thu, 17 Apr 2014 04:23:20 -0400 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 17 Apr 2014 01:23:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,877,1389772800"; d="scan'208";a="522117212" Received: from unknown (HELO localhost.png.intel.com) ([172.30.66.71]) by fmsmga002.fm.intel.com with ESMTP; 17 Apr 2014 01:23:17 -0700 From: Chew Chiau Ee To: Eric Miao , Russell King , Haojian Zhuang , Mark Brown Cc: Chew Chiau Ee , Mika Westerberg , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] spi/pxa2xx-pci: Pass host clock rate info from PCI glue layer Date: Fri, 18 Apr 2014 00:26:07 +0800 Message-Id: <1397751967-20250-3-git-send-email-chiau.ee.chew@intel.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1397751967-20250-1-git-send-email-chiau.ee.chew@intel.com> References: <1397751967-20250-1-git-send-email-chiau.ee.chew@intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chew, Chiau Ee Intel BayTrail PCI mode LPSS devices inclusive of SPI do not rely on common clock framework. Thus, this patch allows the PCI mode SPI host to pass the supported clock rate info to the core layer which eventually used for speed calculation. Signed-off-by: Chew, Chiau Ee --- Documentation/spi/pxa2xx | 3 +++ drivers/spi/spi-pxa2xx-pci.c | 3 +++ drivers/spi/spi-pxa2xx.c | 2 ++ include/linux/spi/pxa2xx_spi.h | 1 + 4 files changed, 9 insertions(+), 0 deletions(-) diff --git a/Documentation/spi/pxa2xx b/Documentation/spi/pxa2xx index 3352f97..3cde429 100644 --- a/Documentation/spi/pxa2xx +++ b/Documentation/spi/pxa2xx @@ -31,6 +31,9 @@ The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See the "PXA2xx Developer Manual" section "Clocks and Power Management". +The "pxa2xx_spi_master.max_clk_rate" field is used to determine the maximum +clock rate supported by the SPI master. + The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of slave device (chips) attached to this SPI master. diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c index c1865c9..24cd938 100644 --- a/drivers/spi/spi-pxa2xx-pci.c +++ b/drivers/spi/spi-pxa2xx-pci.c @@ -17,6 +17,7 @@ struct pxa_spi_info { enum pxa_ssp_type type; int port_id; int num_chipselect; + unsigned long max_clk_rate; int tx_slave_id; int tx_chan_id; int rx_slave_id; @@ -37,6 +38,7 @@ static struct pxa_spi_info spi_info_configs[] = { .type = LPSS_SSP, .port_id = 0, .num_chipselect = 1, + .max_clk_rate = 50000000, .tx_slave_id = 0, .tx_chan_id = 0, .rx_slave_id = 1, @@ -72,6 +74,7 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev, spi_pdata.rx_slave_id = c->rx_slave_id; spi_pdata.rx_chan_id = c->rx_chan_id; spi_pdata.enable_dma = c->rx_slave_id >= 0 && c->tx_slave_id >= 0; + spi_pdata.max_clk_rate = c->max_clk_rate; ssp = &spi_pdata.ssp; ssp->phys_base = pci_resource_start(dev, 0); diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index d0fc8e0..b670371 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1182,6 +1182,8 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) clk_prepare_enable(ssp->clk); drv_data->max_clk_rate = clk_get_rate(ssp->clk); + if (!drv_data->max_clk_rate) + drv_data->max_clk_rate = platform_info->max_clk_rate; /* Load default SSP configuration */ write_SSCR0(0, drv_data->ioaddr); diff --git a/include/linux/spi/pxa2xx_spi.h b/include/linux/spi/pxa2xx_spi.h index 82d5111..967903f 100644 --- a/include/linux/spi/pxa2xx_spi.h +++ b/include/linux/spi/pxa2xx_spi.h @@ -28,6 +28,7 @@ struct pxa2xx_spi_master { u32 clock_enable; u16 num_chipselect; u8 enable_dma; + unsigned long max_clk_rate; /* DMA engine specific config */ int rx_chan_id;