From patchwork Wed Apr 23 10:16:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 4040051 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 45C2EBFF02 for ; Wed, 23 Apr 2014 11:14:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2919C201ED for ; Wed, 23 Apr 2014 11:14:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1BED6201E7 for ; Wed, 23 Apr 2014 11:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751620AbaDWLOl (ORCPT ); Wed, 23 Apr 2014 07:14:41 -0400 Received: from mail-bl2lp0204.outbound.protection.outlook.com ([207.46.163.204]:29534 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751200AbaDWLOb (ORCPT ); Wed, 23 Apr 2014 07:14:31 -0400 Received: from BLUPR03CA036.namprd03.prod.outlook.com (10.141.30.29) by BL2PR03MB417.namprd03.prod.outlook.com (10.141.92.12) with Microsoft SMTP Server (TLS) id 15.0.921.12; Wed, 23 Apr 2014 11:14:24 +0000 Received: from BL2FFO11FD059.protection.gbl (2a01:111:f400:7c09::196) by BLUPR03CA036.outlook.office365.com (2a01:111:e400:879::29) with Microsoft SMTP Server (TLS) id 15.0.921.12 via Frontend Transport; Wed, 23 Apr 2014 11:14:24 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BL2FFO11FD059.mail.protection.outlook.com (10.173.161.187) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Wed, 23 Apr 2014 11:14:24 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3NBDxma008408; Wed, 23 Apr 2014 04:14:20 -0700 From: Huang Shijie To: CC: , , , , , , , Huang Shijie Subject: [PATCH v1 7/7] mtd: fsl-quadspi: add the DDR quad read support Date: Wed, 23 Apr 2014 18:16:55 +0800 Message-ID: <1398248215-26768-8-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: References: X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(189002)(199002)(479174003)(377424004)(47776003)(20776003)(81342001)(62966002)(11926002)(50466002)(93916002)(77096999)(74502001)(74662001)(80022001)(77156001)(48376002)(79102001)(31966008)(81542001)(76176999)(50986999)(99396002)(36756003)(89996001)(44976005)(88136002)(33646001)(76482001)(46102001)(92726001)(92566001)(83322001)(19580395003)(87936001)(19580405001)(50226001)(83072002)(6806004)(77982001)(87286001)(4396001)(85852003)(80976001)(42262001); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2PR03MB417; H:az84smr01.freescale.net; FPR:A8F3E050.1C65B80F.29E8A176.408BFD43.20577; MLV:sfv; PTR:gate-az5.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01901B3451 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add the DDR quad read support for the fsl-quadspi driver. (1) Test this patch with imx6sx-sdb board (Spansion s25fl128s) The clock rate is 66MHz. (2) The information of NOR flash: ----------------------------------------------- root@imx6qdlsolo:~# mtdinfo /dev/mtd0 mtd0 Name: 21e4000.qspi Type: nor Eraseblock size: 65536 bytes, 64.0 KiB Amount of eraseblocks: 256 (16777216 bytes, 16.0 MiB) Minimum input/output unit size: 1 byte Sub-page size: 1 byte Character device major/minor: 90:0 Bad blocks are allowed: false Device is writable: true ----------------------------------------------- (3) Test this patch set with UBIFS & bonnie++: ----------------------------------------------- ubiattach /dev/ubi_ctrl -m 0 ubimkvol /dev/ubi0 -N test -m mount -t ubifs ubi0:test tmp bonnie++ -d tmp -u 0 -s 10 -r 5 ----------------------------------------------- (4) Test this patch with mtd_speedtest.ko root@imx6qdlsolo:~# insmod mtd_speedtest.ko dev=0 ================================================= mtd_speedtest: MTD device: 0 mtd_speedtest: not NAND flash, assume page size is 512 bytes. mtd_speedtest: MTD device size 16777216, eraseblock size 65536, page size 512, count of eraseblocks 256, pages per eraseblock 128, OOB size 0 mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 665 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 49799 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 662 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 24236 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 657 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 32637 KiB/s mtd_speedtest: Testing erase speed mtd_speedtest: erase speed is 518 KiB/s mtd_speedtest: Testing 2x multi-block erase speed mtd_speedtest: 2x multi-block erase speed is 506 KiB/s mtd_speedtest: Testing 4x multi-block erase speed mtd_speedtest: 4x multi-block erase speed is 503 KiB/s mtd_speedtest: Testing 8x multi-block erase speed mtd_speedtest: 8x multi-block erase speed is 501 KiB/s mtd_speedtest: Testing 16x multi-block erase speed mtd_speedtest: 16x multi-block erase speed is 498 KiB/s mtd_speedtest: Testing 32x multi-block erase speed mtd_speedtest: 32x multi-block erase speed is 496 KiB/s mtd_speedtest: Testing 64x multi-block erase speed mtd_speedtest: 64x multi-block erase speed is 495 KiB/s mtd_speedtest: finished ================================================= (5) Conclusion: The DDR quad read could be 49799 KiB/s. Signed-off-by: Huang Shijie --- drivers/mtd/spi-nor/fsl-quadspi.c | 59 ++++++++++++++++++++++++++++++++++-- 1 files changed, 55 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 0a2901e..fcb963f 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -29,6 +29,9 @@ /* The registers */ #define QUADSPI_MCR 0x00 +#define MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_SHIFT 29 +#define MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_MASK \ + (1 << MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_SHIFT) #define QUADSPI_MCR_RESERVED_SHIFT 16 #define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT) #define QUADSPI_MCR_MDIS_SHIFT 14 @@ -292,7 +295,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) for (i = 0; i < QUADSPI_LUT_NUM; i++) writel(0, base + QUADSPI_LUT_BASE + i * 4); - /* Quad Read */ + /* Quad Read and DDR Quad Read*/ lut_base = SEQID_QUAD_READ * 4; op = nor->read_opcode; dm = nor->read_dummy; @@ -308,6 +311,24 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) dev_err(nor->dev, "Unsupported cmd:%.2x\n", nor->read_opcode); } + } else if (nor->flash_read == SPI_NOR_DDR_QUAD) { + if (op == SPINOR_OP_READ_1_4_4_D || + op == SPINOR_OP_READ4_1_4_4_D) { + /* read mode : 1-4-4, such as Spansion s25fl128s. */ + writel(LUT0(CMD, PAD1, op) + | LUT1(ADDR_DDR, PAD4, addrlen), + base + QUADSPI_LUT(lut_base)); + + writel(LUT0(MODE_DDR, PAD1, 4) | LUT1(DUMMY, PAD1, dm), + base + QUADSPI_LUT(lut_base + 1)); + + writel(LUT0(READ_DDR, PAD4, rxfifo) + | LUT1(JMP_ON_CS, PAD1, 0), + base + QUADSPI_LUT(lut_base + 2)); + } else { + dev_err(nor->dev, + "Unsupported cmd:%.2x\n", nor->read_opcode); + } } /* Write enable */ @@ -369,6 +390,9 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { + case SPINOR_OP_READ_1_4_4_D: + case SPINOR_OP_READ4_1_4_4_D: + case SPINOR_OP_READ4_1_1_4: case SPINOR_OP_READ_1_1_4: return SEQID_QUAD_READ; case SPINOR_OP_WREN: @@ -558,6 +582,8 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q) static void fsl_qspi_init_abh_read(struct fsl_qspi *q) { void __iomem *base = q->iobase; + struct spi_nor *nor = &q->nor[0]; + u32 reg, reg2; int seqid; /* AHB configuration for access buffer 0/1/2 .*/ @@ -572,9 +598,30 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) writel(0, base + QUADSPI_BUF2IND); /* Set the default lut sequence for AHB Read. */ - seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode); + seqid = fsl_qspi_get_seqid(q, nor->read_opcode); writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT, q->iobase + QUADSPI_BFGENCR); + + /* enable the DDR quad read */ + if (nor->flash_read == SPI_NOR_DDR_QUAD) { + reg = readl(q->iobase + QUADSPI_MCR); + + /* Firstly, disable the module */ + writel(reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); + + /* Set the Sampling Register for DDR */ + reg2 = readl(q->iobase + QUADSPI_SMPR); + reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK; + reg2 |= (2 << QUADSPI_SMPR_DDRSMP_SHIFT); + writel(reg2, q->iobase + QUADSPI_SMPR); + + /* Enable the module again (enable the DDR too) */ + reg |= QUADSPI_MCR_DDR_EN_MASK; + if (is_imx6sx_qspi(q)) + reg |= MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_MASK; + + writel(reg, q->iobase + QUADSPI_MCR); + } } /* We use this function to do some basic init for spi_nor_scan(). */ @@ -863,6 +910,7 @@ static int fsl_qspi_probe(struct platform_device *pdev) /* iterate the subnodes. */ for_each_available_child_of_node(dev->of_node, np) { const struct spi_device_id *id; + enum read_mode mode = SPI_NOR_QUAD; char modalias[40]; u32 dummy = 0; @@ -903,13 +951,16 @@ static int fsl_qspi_probe(struct platform_device *pdev) /* Set the dummy cycles for the DDR Quad Read */ ret = of_property_read_u32(np, "spi-nor,ddr-quad-read-dummy", &dummy); - if (!ret && dummy > 0 && dummy < 8) + if (!ret && dummy > 0 && dummy < 8) { nor->read_dummy = dummy; + mode = SPI_NOR_DDR_QUAD; + dev_dbg(dev, "The DDR quad read dummy is %d.\n", dummy); + } /* set the chip address for READID */ fsl_qspi_set_base_addr(q, nor); - ret = spi_nor_scan(nor, id, SPI_NOR_QUAD); + ret = spi_nor_scan(nor, id, mode); if (ret) goto map_failed;