From patchwork Mon Apr 28 03:53:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 4075091 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9E511BFF02 for ; Mon, 28 Apr 2014 05:07:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B470920204 for ; Mon, 28 Apr 2014 05:07:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A4C2B20200 for ; Mon, 28 Apr 2014 05:07:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753128AbaD1FHI (ORCPT ); Mon, 28 Apr 2014 01:07:08 -0400 Received: from mail-bl2lp0207.outbound.protection.outlook.com ([207.46.163.207]:32767 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753038AbaD1FHH (ORCPT ); Mon, 28 Apr 2014 01:07:07 -0400 Received: from BLUPR03CA036.namprd03.prod.outlook.com (10.141.30.29) by BLUPR03MB423.namprd03.prod.outlook.com (10.141.78.150) with Microsoft SMTP Server (TLS) id 15.0.929.12; Mon, 28 Apr 2014 04:52:32 +0000 Received: from BN1AFFO11FD021.protection.gbl (2a01:111:f400:7c10::130) by BLUPR03CA036.outlook.office365.com (2a01:111:e400:879::29) with Microsoft SMTP Server (TLS) id 15.0.921.12 via Frontend Transport; Mon, 28 Apr 2014 04:52:33 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BN1AFFO11FD021.mail.protection.outlook.com (10.58.52.81) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Mon, 28 Apr 2014 04:52:32 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3S4pr3e009014; Sun, 27 Apr 2014 21:52:29 -0700 From: Huang Shijie To: CC: , , , , , , , Huang Shijie Subject: [PATCH v2 10/10] mtd: fsl-quadspi: add DDR quad read support for Micron Date: Mon, 28 Apr 2014 11:53:47 +0800 Message-ID: <1398657227-20721-11-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: <1398657227-20721-1-git-send-email-b32955@freescale.com> References: <1398657227-20721-1-git-send-email-b32955@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(189002)(199002)(377424004)(87286001)(99396002)(50466002)(93916002)(77096999)(77156001)(88136002)(81542001)(36756003)(48376002)(76482001)(76176999)(80976001)(31966008)(74662001)(74502001)(80022001)(50226001)(4396001)(20776003)(79102001)(83072002)(46102001)(92726001)(87936001)(33646001)(81342001)(77982001)(44976005)(19580405001)(89996001)(85852003)(62966002)(19580395003)(83322001)(6806004)(47776003)(92566001)(42262001); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR03MB423; H:az84smr01.freescale.net; FPR:C8D9D4D4.EC353A59.ED92966.984B32A1.2027B; MLV:sfv; PTR:gate-az5.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01952C6E96 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add DDR quad read opcode and LUT sequence for Micron N25Q256A. The performace : ================================================= mtd_speedtest: MTD device: 1 mtd_speedtest: not NAND flash, assume page size is 512 bytes. mtd_speedtest: MTD device size 33554432, eraseblock size 65536, page size 512, count of eraseblocks 512, pages per eraseblock 128, OOB size 0 mtd_speedtest: testing eraseblock write speed mtd_speedtest: eraseblock write speed is 2426 KiB/s mtd_speedtest: testing eraseblock read speed mtd_speedtest: eraseblock read speed is 32157 KiB/s mtd_speedtest: testing page write speed mtd_speedtest: page write speed is 2362 KiB/s mtd_speedtest: testing page read speed mtd_speedtest: page read speed is 17741 KiB/s mtd_speedtest: testing 2 page write speed mtd_speedtest: 2 page write speed is 2384 KiB/s mtd_speedtest: testing 2 page read speed mtd_speedtest: 2 page read speed is 24058 KiB/s mtd_speedtest: Testing erase speed mtd_speedtest: erase speed is 1927529 KiB/s mtd_speedtest: Testing 2x multi-block erase speed mtd_speedtest: 2x multi-block erase speed is 2184533 KiB/s mtd_speedtest: Testing 4x multi-block erase speed mtd_speedtest: 4x multi-block erase speed is 2184533 KiB/s mtd_speedtest: Testing 8x multi-block erase speed mtd_speedtest: 8x multi-block erase speed is 2340571 KiB/s mtd_speedtest: Testing 16x multi-block erase speed mtd_speedtest: 16x multi-block erase speed is 2340571 KiB/s mtd_speedtest: Testing 32x multi-block erase speed mtd_speedtest: 32x multi-block erase speed is 2340571 KiB/s mtd_speedtest: Testing 64x multi-block erase speed mtd_speedtest: 64x multi-block erase speed is 2340571 KiB/s mtd_speedtest: finished ================================================= Signed-off-by: Huang Shijie --- drivers/mtd/spi-nor/fsl-quadspi.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index a5dbc62..08944cb 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -325,6 +325,18 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) writel(LUT0(READ_DDR, PAD4, rxfifo) | LUT1(JMP_ON_CS, PAD1, 0), base + QUADSPI_LUT(lut_base + 2)); + } else if (op == SPINOR_OP_READ_1_1_4_D) { + /* read mode : 1-1-4, such as Micron N25Q256A. */ + writel(LUT0(CMD, PAD1, op) + | LUT1(ADDR_DDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + + writel(LUT0(DUMMY, PAD1, dm) + | LUT1(READ_DDR, PAD4, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + + writel(LUT0(JMP_ON_CS, PAD1, 0), + base + QUADSPI_LUT(lut_base + 2)); } else { dev_err(nor->dev, "Unsupported opcode : 0x%.2x\n", op); } @@ -389,6 +401,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd) { switch (cmd) { + case SPINOR_OP_READ_1_1_4_D: case SPINOR_OP_READ_1_4_4_D: case SPINOR_OP_READ4_1_4_4_D: case SPINOR_OP_READ4_1_1_4: