From patchwork Mon Jun 2 19:46:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chew Chiau Ee X-Patchwork-Id: 4281241 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D773ABEEA7 for ; Mon, 2 Jun 2014 11:44:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1B604203B0 for ; Mon, 2 Jun 2014 11:44:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 47F09203B5 for ; Mon, 2 Jun 2014 11:44:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754126AbaFBLoX (ORCPT ); Mon, 2 Jun 2014 07:44:23 -0400 Received: from mga03.intel.com ([143.182.124.21]:30334 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753996AbaFBLoW (ORCPT ); Mon, 2 Jun 2014 07:44:22 -0400 Received: from azsmga001.ch.intel.com ([10.2.17.19]) by azsmga101.ch.intel.com with ESMTP; 02 Jun 2014 04:44:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.98,956,1392192000"; d="scan'208";a="439803194" Received: from unknown (HELO localhost.png.intel.com) ([10.221.118.140]) by azsmga001.ch.intel.com with ESMTP; 02 Jun 2014 04:43:58 -0700 From: Chew Chiau Ee To: Eric Miao , Russell King , Haojian Zhuang , Mark Brown , Grant Likely , Rob Herring Cc: Darren Hart , Mika Westerberg , LKML , linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, Chew Chiau Ee Subject: [PATCH 1/2] spi/pxa2xx-pci: Add common clock framework support in PCI glue layer Date: Tue, 3 Jun 2014 03:46:18 +0800 Message-Id: <1401738379-4107-2-git-send-email-chiau.ee.chew@intel.com> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1401738379-4107-1-git-send-email-chiau.ee.chew@intel.com> References: <1401738379-4107-1-git-send-email-chiau.ee.chew@intel.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, DATE_IN_FUTURE_06_12, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chew, Chiau Ee SPI PXA2XX core layer has dependency on common clock framework to obtain information on host supported clock rate. Thus, we setup the clock device in the PCI glue layer to enable PCI mode host pass in the clock rate information. Signed-off-by: Chew, Chiau Ee --- drivers/spi/spi-pxa2xx-pci.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c index c1865c9..11adc9b 100644 --- a/drivers/spi/spi-pxa2xx-pci.c +++ b/drivers/spi/spi-pxa2xx-pci.c @@ -7,6 +7,9 @@ #include #include #include +#include +#include +#include enum { PORT_CE4100, @@ -21,6 +24,7 @@ struct pxa_spi_info { int tx_chan_id; int rx_slave_id; int rx_chan_id; + unsigned long max_clk_rate; }; static struct pxa_spi_info spi_info_configs[] = { @@ -32,6 +36,7 @@ static struct pxa_spi_info spi_info_configs[] = { .tx_chan_id = -1, .rx_slave_id = -1, .rx_chan_id = -1, + .max_clk_rate = 3686400, }, [PORT_BYT] = { .type = LPSS_SSP, @@ -41,6 +46,7 @@ static struct pxa_spi_info spi_info_configs[] = { .tx_chan_id = 0, .rx_slave_id = 1, .rx_chan_id = 1, + .max_clk_rate = 50000000, }, }; @@ -53,6 +59,7 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev, struct pxa2xx_spi_master spi_pdata; struct ssp_device *ssp; struct pxa_spi_info *c; + struct clk *clk; ret = pcim_enable_device(dev); if (ret) @@ -84,6 +91,19 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev, ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn; ssp->type = c->type; + clk = clk_register_fixed_rate(&dev->dev, "spi_pxa2xx_clk", NULL, + CLK_IS_ROOT, c->max_clk_rate); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + clk_register_clkdev(clk, NULL, dev_name(&dev->dev)); + + ssp->clk = devm_clk_get(&dev->dev, NULL); + if (IS_ERR(ssp->clk)) { + dev_err(&dev->dev, "failed to get clock\n"); + return PTR_ERR(ssp->clk); + } + memset(&pi, 0, sizeof(pi)); pi.parent = &dev->dev; pi.name = "pxa2xx-spi";