diff mbox

[2/2] spi: cadence: Fix 3-to-8 mux mode

Message ID 1417101138-2619-2-git-send-email-lars@metafoo.de (mailing list archive)
State Accepted
Commit ee0ebe81004bd0bedf7abe8a2f3eb745da0264dc
Headers show

Commit Message

Lars-Peter Clausen Nov. 27, 2014, 3:12 p.m. UTC 
In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the
control register. Currently the driver never sets this bit even when
configured for 3-to-8 mux mode. This patch adds code which sets the bit
during device initialization when necessary.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/spi/spi-cadence.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

Comments

Harini Katakam Nov. 28, 2014, 6:52 a.m. UTC | #1 
On Thu, Nov 27, 2014 at 8:42 PM, Lars-Peter Clausen <lars@metafoo.de> wrote:
> In 3-to-8 mux mode for the CS pins we need to set the PERI_SEL bit in the
> control register. Currently the driver never sets this bit even when
> configured for 3-to-8 mux mode. This patch adds code which sets the bit
> during device initialization when necessary.
>
> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

Acked-by: Harini Katakam <harinik@xilinx.com>

Regards,
Harini
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diff mbox

Patch

diff --git a/drivers/spi/spi-cadence.c b/drivers/spi/spi-cadence.c
index 2404937..5a67498 100644
--- a/drivers/spi/spi-cadence.c
+++ b/drivers/spi/spi-cadence.c
@@ -47,6 +47,7 @@ 
 #define CDNS_SPI_CR_CPHA_MASK		0x00000004 /* Clock Phase Control */
 #define CDNS_SPI_CR_CPOL_MASK		0x00000002 /* Clock Polarity Control */
 #define CDNS_SPI_CR_SSCTRL_MASK		0x00003C00 /* Slave Select Mask */
+#define CDNS_SPI_CR_PERI_SEL_MASK	0x00000200 /* Peripheral Select Decode */
 #define CDNS_SPI_CR_BAUD_DIV_MASK	0x00000038 /* Baud Rate Divisor Mask */
 #define CDNS_SPI_CR_MSTREN_MASK		0x00000001 /* Master Enable Mask */
 #define CDNS_SPI_CR_MANSTRTEN_MASK	0x00008000 /* Manual TX Enable Mask */
@@ -148,6 +149,11 @@  static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
  */
 static void cdns_spi_init_hw(struct cdns_spi *xspi)
 {
+	u32 ctrl_reg = CDNS_SPI_CR_DEFAULT_MASK;
+
+	if (xspi->is_decoded_cs)
+		ctrl_reg |= CDNS_SPI_CR_PERI_SEL_MASK;
+
 	cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
 		       CDNS_SPI_ER_DISABLE_MASK);
 	cdns_spi_write(xspi, CDNS_SPI_IDR_OFFSET,
@@ -160,8 +166,7 @@  static void cdns_spi_init_hw(struct cdns_spi *xspi)
 
 	cdns_spi_write(xspi, CDNS_SPI_ISR_OFFSET,
 		       CDNS_SPI_IXR_ALL_MASK);
-	cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET,
-		       CDNS_SPI_CR_DEFAULT_MASK);
+	cdns_spi_write(xspi, CDNS_SPI_CR_OFFSET, ctrl_reg);
 	cdns_spi_write(xspi, CDNS_SPI_ER_OFFSET,
 		       CDNS_SPI_ER_ENABLE_MASK);
 }