From patchwork Fri Mar 6 23:46:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tthayer@opensource.altera.com X-Patchwork-Id: 5958141 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8B68ABF440 for ; Fri, 6 Mar 2015 23:46:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8DE8420397 for ; Fri, 6 Mar 2015 23:46:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6C1982038F for ; Fri, 6 Mar 2015 23:46:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755235AbbCFXqg (ORCPT ); Fri, 6 Mar 2015 18:46:36 -0500 Received: from mail-bn1on0086.outbound.protection.outlook.com ([157.56.110.86]:46160 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751648AbbCFXqf (ORCPT ); Fri, 6 Mar 2015 18:46:35 -0500 Received: from tthayer-HP-Z620-Ubuntu.altera.com (64.129.157.38) by BLUPR03MB423.namprd03.prod.outlook.com (10.141.78.150) with Microsoft SMTP Server (TLS) id 15.1.106.11; Fri, 6 Mar 2015 23:46:31 +0000 From: To: , , , , , , , CC: , , , , , , , , , Subject: [RFC/PATCHv2 3/3] spi: dw-spi: Pointers select 16b vs. 32b DesignWare access Date: Fri, 6 Mar 2015 17:46:34 -0600 Message-ID: <1425685594-26595-4-git-send-email-tthayer@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1425685594-26595-1-git-send-email-tthayer@opensource.altera.com> References: <1425685594-26595-1-git-send-email-tthayer@opensource.altera.com> MIME-Version: 1.0 X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BY2PR06CA062.namprd06.prod.outlook.com (10.141.250.180) To BLUPR03MB423.namprd03.prod.outlook.com (10.141.78.150) Authentication-Results: kernel.org; dkim=none (message not signed) header.d=none; X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB423; X-Forefront-Antispam-Report: BMV:1; SFV:NSPM; SFS:(10009020)(6009001)(76176999)(66066001)(50986999)(47776003)(86152002)(87976001)(551934003)(229853001)(33646002)(2201001)(92566002)(77156002)(62966003)(122386002)(50466002)(19580395003)(42186005)(46102003)(86362001)(40100003)(19580405001)(50226001)(48376002)(2950100001)(53416004)(77096005); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR03MB423; H:tthayer-HP-Z620-Ubuntu.altera.com; FPR:; SPF:None; MLV:sfv; LANG:en; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5002008)(5005006); SRVR:BLUPR03MB423; BCL:0; PCL:0; RULEID:; SRVR:BLUPR03MB423; X-Forefront-PRVS: 05079D8470 X-OriginatorOrg: opensource.altera.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2015 23:46:31.0982 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB423 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Thor Thayer Altera's Arria10 SoC interconnect requires a 32 bit write for APB peripherals. The current spi-dw driver uses 16bit accesses in some locations. Use function pointers to support 32 bit accesses but retain legacy 16 bit access. Signed-off-by: Thor Thayer --- drivers/spi/spi-dw-mmio.c | 7 ++++++- drivers/spi/spi-dw.c | 29 +++++++++++++++++------------ drivers/spi/spi-dw.h | 12 ++++++++++++ 3 files changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..c4fe9e9 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -76,8 +76,13 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) num_cs = 4; - if (pdev->dev.of_node) + if (pdev->dev.of_node) { of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); + if (of_property_read_bool(pdev->dev.of_node, "32bit_access")) { + dws->read_w = dw_readw32; + dws->write_w = dw_writew32; + } + } dws->num_cs = num_cs; diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index c5fa2be..d008791 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -157,7 +157,7 @@ static inline u32 tx_max(struct dw_spi *dws) u32 tx_left, tx_room, rxtx_gap; tx_left = (dws->tx_end - dws->tx) / dws->n_bytes; - tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR); + tx_room = dws->fifo_len - dws->read_w(dws, DW_SPI_TXFLR); /* * Another concern is about the tx/rx mismatch, we @@ -178,7 +178,7 @@ static inline u32 rx_max(struct dw_spi *dws) { u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes; - return min_t(u32, rx_left, dw_readw(dws, DW_SPI_RXFLR)); + return min_t(u32, rx_left, dws->read_w(dws, DW_SPI_RXFLR)); } static void dw_writer(struct dw_spi *dws) @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writew(dws, DW_SPI_DR, txw); + dws->write_w(dws, DW_SPI_DR, txw); dws->tx += dws->n_bytes; } } @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readw(dws, DW_SPI_DR); + rxw = dws->read_w(dws, DW_SPI_DR); /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) @@ -254,11 +254,11 @@ static void int_error_stop(struct dw_spi *dws, const char *msg) static irqreturn_t interrupt_transfer(struct dw_spi *dws) { - u16 irq_status = dw_readw(dws, DW_SPI_ISR); + u16 irq_status = dws->read_w(dws, DW_SPI_ISR); /* Error handling */ if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) { - dw_readw(dws, DW_SPI_ICR); + dws->read_w(dws, DW_SPI_ICR); int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun"); return IRQ_HANDLED; } @@ -283,7 +283,7 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id) { struct spi_master *master = dev_id; struct dw_spi *dws = spi_master_get_devdata(master); - u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f; + u16 irq_status = dws->read_w(dws, DW_SPI_ISR) & 0x3f; if (!irq_status) return IRQ_NONE; @@ -379,7 +379,7 @@ static int dw_spi_transfer_one(struct spi_master *master, cr0 |= (chip->tmode << SPI_TMOD_OFFSET); } - dw_writew(dws, DW_SPI_CTRL0, cr0); + dws->write_w(dws, DW_SPI_CTRL0, cr0); /* Check if current transfer is a DMA transaction */ dws->dma_mapped = map_dma_buffers(master, spi, transfer); @@ -393,7 +393,7 @@ static int dw_spi_transfer_one(struct spi_master *master, */ if (!dws->dma_mapped && !chip->poll_mode) { txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes); - dw_writew(dws, DW_SPI_TXFLTR, txlevel); + dws->write_w(dws, DW_SPI_TXFLTR, txlevel); /* Set the interrupt mask */ imask |= SPI_INT_TXEI | SPI_INT_TXOI | @@ -516,11 +516,11 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) u32 fifo; for (fifo = 1; fifo < 256; fifo++) { - dw_writew(dws, DW_SPI_TXFLTR, fifo); - if (fifo != dw_readw(dws, DW_SPI_TXFLTR)) + dws->write_w(dws, DW_SPI_TXFLTR, fifo); + if (fifo != dws->read_w(dws, DW_SPI_TXFLTR)) break; } - dw_writew(dws, DW_SPI_TXFLTR, 0); + dws->write_w(dws, DW_SPI_TXFLTR, 0); dws->fifo_len = (fifo == 1) ? 0 : fifo; dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len); @@ -545,6 +545,11 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws) dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60); snprintf(dws->name, sizeof(dws->name), "dw_spi%d", dws->bus_num); + if (!dws->read_w) + dws->read_w = dw_readw; + if (!dws->write_w) + dws->write_w = dw_writew; + ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED, dws->name, master); if (ret < 0) { diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 855bfdd..1df09e2 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -141,6 +141,8 @@ struct dw_spi { #ifdef CONFIG_DEBUG_FS struct dentry *debugfs; #endif + u16 (*read_w)(struct dw_spi *dws, u32 offset); + void (*write_w)(struct dw_spi *dws, u32 offset, u16 val); }; static inline u32 dw_readl(struct dw_spi *dws, u32 offset) @@ -163,6 +165,16 @@ static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) __raw_writew(val, dws->regs + offset); } +static inline u16 dw_readw32(struct dw_spi *dws, u32 offset) +{ + return (u16)__raw_readl(dws->regs + offset); +} + +static inline void dw_writew32(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writel((u32)val, dws->regs + offset); +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));