diff mbox

[v3,2/3] devicetree: spi: fsl-dspi: Add cs-sck delays

Message ID 1428093571-20407-3-git-send-email-aaron.brice@datasoft.com (mailing list archive)
State Accepted
Commit c1c14957afd3026dcbc2e7ca599e6d035c7d8e01
Headers show

Commit Message

Aaron Brice April 3, 2015, 8:39 p.m. UTC 
Adding fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay properties to
support delays before and after starting the clock in a transfer.

Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
---
 Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Mark Brown April 6, 2015, 5:12 p.m. UTC | #1 
On Fri, Apr 03, 2015 at 01:39:30PM -0700, Aaron Brice wrote:
> Adding fsl,spi-cs-sck-delay and fsl,spi-sck-cs-delay properties to
> support delays before and after starting the clock in a transfer.

Applied, please use subject lines matching the style for the subsystem.
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index cbbe16e..70af78a 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -16,6 +16,12 @@  Optional property:
   in big endian mode, otherwise in native mode(same with CPU), for more
   detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
 
+Optional SPI slave node properties:
+- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
+  select and the start of clock signal, at the start of a transfer.
+- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
+  signal and deactivating chip select, at the end of a transfer.
+
 Example:
 
 dspi0@4002c000 {
@@ -43,6 +49,8 @@  dspi0@4002c000 {
 		reg = <0>;
 		linux,modalias = "m25p80";
 		modal = "at26df081a";
+		fsl,spi-cs-sck-delay = <100>;
+		fsl,spi-sck-cs-delay = <50>;
 	};
 };