From patchwork Fri Jun 19 08:43:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael van der Westhuizen X-Patchwork-Id: 6643541 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id E4AD39F358 for ; Fri, 19 Jun 2015 08:44:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E014220966 for ; Fri, 19 Jun 2015 08:44:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C457520964 for ; Fri, 19 Jun 2015 08:44:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754631AbbFSIoe (ORCPT ); Fri, 19 Jun 2015 04:44:34 -0400 Received: from mail-wi0-f182.google.com ([209.85.212.182]:38116 "EHLO mail-wi0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753616AbbFSIoc (ORCPT ); Fri, 19 Jun 2015 04:44:32 -0400 Received: by wibdq8 with SMTP id dq8so11847917wib.1 for ; Fri, 19 Jun 2015 01:44:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z8Fe8YaOOZK5bkX1CguLuLPhPXV2sJtDahF/7apBspA=; b=AEoQAlRNiwszK919mXNTsYp+ar5iQw2GMiGmPiME5qaSIRiGCVytV8m5rHyONpfKHG ACgIunbde5oADUsJCacfMxfthgGvVXJFUBUKwThPzbImwMRasmyLhJKxpsmiZldICTIA xJf4EHWqk2SrGQN3IV+nqZOiazrUChx1YdtsgP48De2tG+DfJJuZX+qkk4ZWu634I0OG Dh/rSi3NCTOhvSMI1gCZhIfbd1oyqjjJamqreabjTUMUPv+XKYB6rdYMq2UG62lndEx7 sB/y6jA743vQCyjG/javKBNWJCdYM+ui0C6IYm6FMI/bgMHDUCzEdbkXprMRnTTKjf0B BPFA== X-Gm-Message-State: ALoCoQk8nAu7gh/iEh8nc4vCH7FR0lpTJg6W7I4DQ+m3iwe8GQ1/ZMyUGwl+pKimyMvQ7fwd41bC X-Received: by 10.194.60.81 with SMTP id f17mr23000986wjr.62.1434703471387; Fri, 19 Jun 2015 01:44:31 -0700 (PDT) Received: from localhost.localdomain (105-237-212-12.access.mtnbusiness.co.za. [105.237.212.12]) by mx.google.com with ESMTPSA id c7sm2420967wjb.19.2015.06.19.01.44.28 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Jun 2015 01:44:30 -0700 (PDT) From: Michael van der Westhuizen To: linux-spi@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Steffen Trumtrar , Thor Thayer , Andy Shevchenko , Mark Brown , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Michael van der Westhuizen Subject: [PATCH 1/2] spi: dw: Allow interface drivers to limit data I/O to word sizes Date: Fri, 19 Jun 2015 10:43:55 +0200 Message-Id: <1434703435-25198-3-git-send-email-michael@smart-africa.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1434703435-25198-1-git-send-email-michael@smart-africa.com> References: <1434703435-25198-1-git-send-email-michael@smart-africa.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-7.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Signed-off-by: Michael van der Westhuizen --- drivers/spi/spi-dw-mmio.c | 5 +++++ drivers/spi/spi-dw.c | 13 +++++++++++-- drivers/spi/spi-dw.h | 11 +++++++++++ 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..1397424 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -74,6 +74,11 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->max_freq = clk_get_rate(dwsmmio->clk); + if (pdev->dev.of_node) + dws->data_io_16bit = + of_property_read_bool(pdev->dev.of_node, + "snps,data-io-16bit"); + num_cs = 4; if (pdev->dev.of_node) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 8d67d03..862b001 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -194,7 +194,12 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writel(dws, DW_SPI_DR, txw); + + if (dws->data_io_16bit) + dw_writew(dws, DW_SPI_DR, txw); + else + dw_writel(dws, DW_SPI_DR, txw); + dws->tx += dws->n_bytes; } } @@ -205,7 +210,11 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readl(dws, DW_SPI_DR); + if (dws->data_io_16bit) + rxw = dw_readw(dws, DW_SPI_DR); + else + rxw = dw_readl(dws, DW_SPI_DR); + /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 6c91391..ced276a 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -109,6 +109,7 @@ struct dw_spi { u32 fifo_len; /* depth of the FIFO buffer */ u32 max_freq; /* max bus freq supported */ + bool data_io_16bit; /* DR is only 16 bits wide */ u16 bus_num; u16 num_cs; /* supported slave numbers */ @@ -145,11 +146,21 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) return __raw_readl(dws->regs + offset); } +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) +{ + return __raw_readw(dws->regs + offset); +} + static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { __raw_writel(val, dws->regs + offset); } +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writew(val, dws->regs + offset); +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));