| Message ID | 1436880205-25023-1-git-send-email-qxovxp@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 1476253cef9dbfc1f7f6a1bd19252ca528cd63bd |
| Headers | show |
On Tue, Jul 14, 2015 at 04:23:25PM +0300, Andrew Y. Kuksov wrote:
> Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3
What is the problem and how does this change fix it (this information
should be in the changelog)?
>> Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3 > What is the problem and how does this change fix it (this information > should be in the changelog)? SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2 and SPI_MODE_3 requires clk high when inactive. Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data Phase Control), SCLK_POL (SPI Clock Polarity Control), SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS Polarity Select) of ECSPIx_CONFIGREG register. This patch allows driver to clear corresponding bits in these fields. -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Jul 14, 2015 at 07:06:36PM +0300, Andrew Kuksov wrote: > >> Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3 > > What is the problem and how does this change fix it (this information > > should be in the changelog)? > SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2 > and SPI_MODE_3 requires clk high when inactive. > Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data > Phase Control), SCLK_POL (SPI Clock Polarity Control), > SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS > Polarity Select) of ECSPIx_CONFIGREG register. > This patch allows driver to clear corresponding bits in these fields. Please provide a patch with a changelog more like this...
On Tue, Jul 14, 2015 at 07:06:36PM +0300, Andrew Kuksov wrote: > >> Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3 > > What is the problem and how does this change fix it (this information > > should be in the changelog)? > SPI_MODE_0 and SPI_MODE_1 requires clock low when inactive. SPI_MODE_2 > and SPI_MODE_3 requires clk high when inactive. > Currently driver can just set bits in fields SCLK_PHA (SPI Clock/Data > Phase Control), SCLK_POL (SPI Clock Polarity Control), > SCLK_CTL (controls the inactive state of SCLK) ans SS_POL (SPI SS > Polarity Select) of ECSPIx_CONFIGREG register. > This patch allows driver to clear corresponding bits in these fields. OK... when I was asking for this to be in the changelog what I meant was that you should send a new patch with a changelog including the relevant description. I've done that by hand now.
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index eb7d3a6..36b6ece 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -335,13 +335,20 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, if (config->mode & SPI_CPHA) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); + else + cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs); if (config->mode & SPI_CPOL) { cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); + } else { + cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs); + cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs); } if (config->mode & SPI_CS_HIGH) cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); + else + cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs); writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
Fixed problem with setting spi mode 0 or 1 after setting mode 2 or 3 Signed-off-by: Andrew Y. Kuksov <qxovxp@gmail.com> --- drivers/spi/spi-imx.c | 7 +++++++ 1 file changed, 7 insertions(+)