From patchwork Tue Aug 18 20:21:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael van der Westhuizen X-Patchwork-Id: 7033521 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 44C059F344 for ; Tue, 18 Aug 2015 20:22:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4F560206D5 for ; Tue, 18 Aug 2015 20:22:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12C96206D9 for ; Tue, 18 Aug 2015 20:22:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753074AbbHRUWj (ORCPT ); Tue, 18 Aug 2015 16:22:39 -0400 Received: from mail-wi0-f177.google.com ([209.85.212.177]:35068 "EHLO mail-wi0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752990AbbHRUWi (ORCPT ); Tue, 18 Aug 2015 16:22:38 -0400 Received: by wicne3 with SMTP id ne3so104284456wic.0 for ; Tue, 18 Aug 2015 13:22:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0O2PyrkDWkHBMyka7n/abJKL7+W89NaUvLOC3EJPpT0=; b=fmeVC30IIUrY2Bs3ISmNCMIcMJVfdlT1pRzMTjj9tT/xZ6BkZUcavWnCaSlWA5W52v i9Yyes0cvWd5zj7qHsjBImqq4Zxwrzvp1dNt+V18vN0wWora5zHLwX/RsH+zMmh/Kwr/ jpPoanEKfaoBEhYzarynr3g7zfXDfmgqIlghetTNPGsCnXv9TGq0z234xmtiYtyps7m5 m6srg1O/cVfneNlrlys9bd1azEXdywRJan3vmnubOKQvCe7NNYSGJp/nQhF9OBZWDu0E jPdutkuApUBrYIgE/JFJMyxOIaYEMqSDQFVLiP1SvlhcpCE6iFT4zra/MbF3kZzXRj1y CT+w== X-Gm-Message-State: ALoCoQnSzWnIStnoy83LrAOOeBs6HwEohRg/y7TQ2t01zUGooitydq+xlDsr+jHaCKsBFUvPKzqV X-Received: by 10.180.92.138 with SMTP id cm10mr46017676wib.33.1439929357315; Tue, 18 Aug 2015 13:22:37 -0700 (PDT) Received: from localhost.localdomain ([105.210.175.110]) by smtp.gmail.com with ESMTPSA id b13sm22806578wic.15.2015.08.18.13.22.32 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Aug 2015 13:22:36 -0700 (PDT) From: Michael van der Westhuizen To: linux-spi@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Steffen Trumtrar , Thor Thayer , Andy Shevchenko , Mark Brown , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Michael van der Westhuizen Subject: [PATCH v3 2/2] spi: dw: Allow interface drivers to limit data I/O to word sizes Date: Tue, 18 Aug 2015 22:21:53 +0200 Message-Id: <1439929313-4948-3-git-send-email-michael@smart-africa.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1439929313-4948-1-git-send-email-michael@smart-africa.com> References: <1439929313-4948-1-git-send-email-michael@smart-africa.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The commit dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") changed all 16bit accesses in the DW_apb_ssi driver to 32bit. This, unfortunately, breaks data register access on picoXcell, where the DW IP needs data register accesses to be word accesses (all other accesses appear to be OK). This change introduces a new master variable to allow interface drivers to specify that 16bit data transfer I/O is required. This change also introduces the ability to set this variable via device tree bindings in the MMIO interface driver. Both the core and the MMIO interface driver default to the current 32bit behaviour. Before this change, on a picoXcell pc3x3: spi_master spi32766: interrupt_transfer: fifo overrun/underrun m25p80 spi32766.0: error -5 reading 9f m25p80: probe of spi32766.0 failed with error -5 After this change: m25p80 spi32766.0: m25p40 (512 Kbytes) Fixes: dd11444327ce ("spi: dw-spi: Convert 16bit accesses to 32bit accesses") Signed-off-by: Michael van der Westhuizen Reviewed-by: Andy Shevchenko --- Changes in v3: - Rename the DT property as requested by Rob Herring. Changes in v2: - Incorporate review feedback from Andy Shevchenko - Rework the DT bindings to accept an I/O register width as a number of bytes rather than using a boolean spefifying the width preference to be 16 bits. - Add data register access wrapper functions and use them when reading and writing the data register. drivers/spi/spi-dw-mmio.c | 3 +++ drivers/spi/spi-dw.c | 4 ++-- drivers/spi/spi-dw.h | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index eb03e12..7edede6 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -74,6 +74,9 @@ static int dw_spi_mmio_probe(struct platform_device *pdev) dws->max_freq = clk_get_rate(dwsmmio->clk); + of_property_read_u32(pdev->dev.of_node, "reg-io-width", + &dws->reg_io_width); + num_cs = 4; if (pdev->dev.of_node) diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 8d67d03..4fbfcdc 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -194,7 +194,7 @@ static void dw_writer(struct dw_spi *dws) else txw = *(u16 *)(dws->tx); } - dw_writel(dws, DW_SPI_DR, txw); + dw_write_io_reg(dws, DW_SPI_DR, txw); dws->tx += dws->n_bytes; } } @@ -205,7 +205,7 @@ static void dw_reader(struct dw_spi *dws) u16 rxw; while (max--) { - rxw = dw_readl(dws, DW_SPI_DR); + rxw = dw_read_io_reg(dws, DW_SPI_DR); /* Care rx only if the transfer's original "rx" is not null */ if (dws->rx_end - dws->len) { if (dws->n_bytes == 1) diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 6c91391..b75ed32 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -109,6 +109,7 @@ struct dw_spi { u32 fifo_len; /* depth of the FIFO buffer */ u32 max_freq; /* max bus freq supported */ + u32 reg_io_width; /* DR I/O width in bytes */ u16 bus_num; u16 num_cs; /* supported slave numbers */ @@ -145,11 +146,45 @@ static inline u32 dw_readl(struct dw_spi *dws, u32 offset) return __raw_readl(dws->regs + offset); } +static inline u16 dw_readw(struct dw_spi *dws, u32 offset) +{ + return __raw_readw(dws->regs + offset); +} + static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val) { __raw_writel(val, dws->regs + offset); } +static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val) +{ + __raw_writew(val, dws->regs + offset); +} + +static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset) +{ + switch (dws->reg_io_width) { + case 2: + return dw_readw(dws, offset); + case 4: + default: + return dw_readl(dws, offset); + } +} + +static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val) +{ + switch (dws->reg_io_width) { + case 2: + dw_writew(dws, offset, val); + break; + case 4: + default: + dw_writel(dws, offset, val); + break; + } +} + static inline void spi_enable_chip(struct dw_spi *dws, int enable) { dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));