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[89.233.200.205]) by smtp.gmail.com with ESMTPSA id tv8sm164546lbb.27.2015.12.05.08.57.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Dec 2015 08:57:23 -0800 (PST) From: Anton Bondarenko To: broonie@kernel.org, b38343@freescale.com, s.hauer@pengutronix.de Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, vladimir_zapolskiy@mentor.com, jiada_wang@mentor.com Subject: [PATCH v5 11/11] spi: imx: add support for all SPI word width for DMA Date: Sat, 5 Dec 2015 17:57:09 +0100 Message-Id: <1449334629-4715-12-git-send-email-anton.bondarenko.sama@gmail.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1449334629-4715-1-git-send-email-anton.bondarenko.sama@gmail.com> References: <1449334629-4715-1-git-send-email-anton.bondarenko.sama@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP DMA transfer for SPI was limited to up to 8 bits word size until now. Sync in SPI burst size and DMA bus width is necessary to correctly support 16 and 32 BPW. Signed-off-by: Anton Bondarenko --- drivers/spi/spi-imx.c | 121 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 95 insertions(+), 26 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index f7ee288..d1b9903 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -88,11 +88,15 @@ struct spi_imx_data { struct completion xfer_done; void __iomem *base; + unsigned long base_phys; + struct clk *clk_per; struct clk *clk_ipg; unsigned long spi_clk; unsigned int spi_bus_clk; + unsigned int bytes_per_word; + unsigned int count; void (*tx)(struct spi_imx_data *); void (*rx)(struct spi_imx_data *); @@ -199,13 +203,32 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin, return 7; } +static int spi_imx_get_bytes_per_word(const int bpw) +{ + return DIV_ROUND_UP(bpw, BITS_PER_BYTE); +} + static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, struct spi_transfer *transfer) { struct spi_imx_data *spi_imx = spi_master_get_devdata(master); + unsigned int bpw = transfer->bits_per_word; + + if (!bpw) + bpw = spi->bits_per_word; - if (spi_imx->dma_is_inited && transfer->len > spi_imx->wml && - (transfer->len % spi_imx->wml) == 0) + bpw = spi_imx_get_bytes_per_word(bpw); + + /* + * We need to use SPI word size in calculation to decide + * if we want to go with DMA or PIO mode. Just a short example: + * We need to transfer 24 SPI words with BPW == 32. This will take + * 24 PIO writes to FIFO (and same for reads). But transfer->len will + * be 24*4=96 bytes. WML is 32 SPI words. The decision will be incorrect + * if we do not take into account SPI bits per word. + */ + if (spi_imx->dma_is_inited && transfer->len > (spi_imx->wml * bpw) && + (transfer->len % (spi_imx->wml * bpw)) == 0) return true; return false; } @@ -784,11 +807,60 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id) return IRQ_HANDLED; } +static int spi_imx_sdma_configure(struct spi_master *master) +{ + int ret; + enum dma_slave_buswidth dsb_default = DMA_SLAVE_BUSWIDTH_1_BYTE; + struct dma_slave_config slave_config = {}; + struct spi_imx_data *spi_imx = spi_master_get_devdata(master); + + switch (spi_imx->bytes_per_word) { + case 4: + dsb_default = DMA_SLAVE_BUSWIDTH_4_BYTES; + break; + case 2: + dsb_default = DMA_SLAVE_BUSWIDTH_2_BYTES; + break; + case 1: + dsb_default = DMA_SLAVE_BUSWIDTH_1_BYTE; + break; + default: + pr_err("Not supported word size %d\n", spi_imx->bytes_per_word); + ret = -EINVAL; + goto err; + } + + slave_config.direction = DMA_MEM_TO_DEV; + slave_config.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; + slave_config.dst_addr_width = dsb_default; + slave_config.dst_maxburst = spi_imx->wml; + ret = dmaengine_slave_config(master->dma_tx, &slave_config); + if (ret) { + pr_err("error in TX dma configuration.\n"); + goto err; + } + + memset(&slave_config, 0, sizeof(slave_config)); + + slave_config.direction = DMA_DEV_TO_MEM; + slave_config.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; + slave_config.src_addr_width = dsb_default; + slave_config.src_maxburst = spi_imx->wml; + ret = dmaengine_slave_config(master->dma_rx, &slave_config); + if (ret) + pr_err("error in RX dma configuration.\n"); + +err: + return ret; +} + static int spi_imx_setupxfer(struct spi_device *spi, struct spi_transfer *t) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); struct spi_imx_config config; + unsigned int new_bytes_per_word; + int ret = 0; config.bpw = t ? t->bits_per_word : spi->bits_per_word; config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; @@ -812,9 +884,19 @@ static int spi_imx_setupxfer(struct spi_device *spi, spi_imx->tx = spi_imx_buf_tx_u32; } - spi_imx->devtype_data->config(spi_imx, &config); + new_bytes_per_word = spi_imx_get_bytes_per_word(config.bpw); + if (spi_imx->dma_is_inited && + spi_imx->bytes_per_word != new_bytes_per_word) { + spi_imx->bytes_per_word = new_bytes_per_word; + ret = spi_imx_sdma_configure(spi->master); + if (ret != 0) + pr_err("Can't configure SDMA, error %d\n", ret); + } - return 0; + if (!ret) + ret = spi_imx->devtype_data->config(spi_imx, &config); + + return ret; } static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) @@ -838,7 +920,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, struct spi_master *master, const struct resource *res) { - struct dma_slave_config slave_config = {}; int ret; /* use pio mode for i.mx6dl chip TKT238285 */ @@ -856,16 +937,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, goto err; } - slave_config.direction = DMA_MEM_TO_DEV; - slave_config.dst_addr = res->start + MXC_CSPITXDATA; - slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; - slave_config.dst_maxburst = spi_imx->wml; - ret = dmaengine_slave_config(master->dma_tx, &slave_config); - if (ret) { - dev_err(dev, "error in TX dma configuration.\n"); - goto err; - } - /* Prepare for RX : */ master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); if (IS_ERR(master->dma_rx)) { @@ -875,22 +946,20 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, goto err; } - slave_config.direction = DMA_DEV_TO_MEM; - slave_config.src_addr = res->start + MXC_CSPIRXDATA; - slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; - slave_config.src_maxburst = spi_imx->wml; - ret = dmaengine_slave_config(master->dma_rx, &slave_config); - if (ret) { - dev_err(dev, "error in RX dma configuration.\n"); - goto err; - } - init_completion(&spi_imx->dma_rx_completion); init_completion(&spi_imx->dma_tx_completion); master->can_dma = spi_imx_can_dma; master->max_dma_len = MAX_SDMA_BD_BYTES; spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; + spi_imx->bytes_per_word = 1; + spi_imx->base_phys = res->start; + ret = spi_imx_sdma_configure(master); + if (ret) { + dev_info(dev, "cannot get setup DMA.\n"); + goto err; + } + spi_imx->dma_is_inited = 1; return 0; @@ -992,7 +1061,7 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, dmaengine_terminate_all(master->dma_rx); } else { transfer_timeout = spi_imx_calculate_timeout(spi_imx, - spi_imx->wml); + spi_imx->bytes_per_word * spi_imx->wml); timeout = wait_for_completion_timeout( &spi_imx->dma_rx_completion, transfer_timeout); if (!timeout) {