From patchwork Mon Dec 14 13:09:42 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ranjit Waghmode X-Patchwork-Id: 7844601 Return-Path: X-Original-To: patchwork-linux-spi@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 668659F350 for ; Mon, 14 Dec 2015 13:26:12 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81B0E203C0 for ; Mon, 14 Dec 2015 13:26:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 877E9203B4 for ; Mon, 14 Dec 2015 13:26:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932403AbbLNN0I (ORCPT ); Mon, 14 Dec 2015 08:26:08 -0500 Received: from mail-cys01nam02on0056.outbound.protection.outlook.com ([104.47.37.56]:48928 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932336AbbLNN0E (ORCPT ); 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Mon, 14 Dec 2015 05:11:09 -0800 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1a8SuD-0002dv-9O; Mon, 14 Dec 2015 05:11:09 -0800 Received: from xsj-pvapsmtp01 (xsj-pvapsmtp01.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id tBEDB37a008078; Mon, 14 Dec 2015 05:11:03 -0800 Received: from [172.23.64.207] (helo=xhd-lin64re117.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1a8Su6-0002Zp-NC; Mon, 14 Dec 2015 05:11:02 -0800 Received: by xhd-lin64re117.xilinx.com (Postfix, from userid 32810) id E5A5720903; Mon, 14 Dec 2015 18:41:01 +0530 (IST) From: Ranjit Waghmode To: , , , , , , , , , , , , , , , , CC: , , , , , , , "Ranjit Waghmode" Subject: [LINUX RFC v3 1/4] spi: addng support for data stripe feature in core Date: Mon, 14 Dec 2015 18:39:42 +0530 Message-ID: <1450098585-3129-2-git-send-email-ranjit.waghmode@xilinx.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1450098585-3129-1-git-send-email-ranjit.waghmode@xilinx.com> References: <1450098585-3129-1-git-send-email-ranjit.waghmode@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-22000.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:149.199.60.100; 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X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(2401047)(520078)(5005006)(8121501046)(3002001)(10201501046); SRVR:BL2NAM02HT254; BCL:0; PCL:0; RULEID:; SRVR:BL2NAM02HT254; X-Forefront-PRVS: 0790FB1F33 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Dec 2015 13:11:10.1603 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL2NAM02HT254 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch enables data stripe feature in spi core. This feature is required to support dual parallel mode of ZynqMP GQSPI controller. To achieve the same an API SPI_MASTER_DATA_STRIPE is added. With data stripe enabled, - even bytes i.e. 0, 2, 4,... are transmitted on lower data bus - odd bytes i.e. 1, 3, 5,.. are transmitted on upper data bus. To support data stripe; need to assert both chip selects once. This is achieved throught API SPI_MASTER_BOTH_CS. Signed-off-by: Ranjit Waghmode --- V3 Changes: - Updated comments for newly added APIs. - Changed patch description for ease of understanding V2 Changes: - Added error handling condition for newly added features --- drivers/spi/spi.c | 8 ++++++++ include/linux/spi/spi.h | 11 +++++++++++ 2 files changed, 19 insertions(+) -- 2.1.2 -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 2b0a8ec..930dac3 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2106,6 +2106,14 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) if (list_empty(&message->transfers)) return -EINVAL; + /* + * Data stripe option is selected if and only if when + * two chips are enabled + */ + if ((master->flags & SPI_MASTER_DATA_STRIPE) + && !(master->flags & SPI_MASTER_BOTH_CS)) + return -EINVAL; + /* Half-duplex links include original MicroWire, and ones with * only one data pin like SPI_3WIRE (switches direction) or where * either MOSI or MISO is missing. They can also be caused by diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index cce80e6..e83b667 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -424,6 +424,17 @@ struct spi_master { #define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */ #define SPI_MASTER_MUST_RX BIT(3) /* requires rx */ #define SPI_MASTER_MUST_TX BIT(4) /* requires tx */ + /* Controller may support data stripe feature when more than one + * chips are present. + * Setting data stripe will send data in following manner: + * -> even bytes i.e. 0, 2, 4,... are transmitted on lower data bus + * -> odd bytes i.e. 1, 3, 5,.. are transmitted on upper data bus + */ +#define SPI_MASTER_DATA_STRIPE BIT(7) /* support data stripe */ + /* Controller may support asserting more than one chip select at once. + * This flag will enable that feature. + */ +#define SPI_MASTER_BOTH_CS BIT(8) /* assert both chip selects */ /* lock and mutex for SPI bus locking */ spinlock_t bus_lock_spinlock;