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PCL:0; RULEID:(601004)(2401047)(13015025)(13024025)(13017025)(5005006)(13018025)(13023025)(8121501046)(10201501046)(3002001); SRVR:SN1NAM02HT175; BCL:0; PCL:0; RULEID:; SRVR:SN1NAM02HT175; X-Forefront-PRVS: 0876988AF0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2016 08:47:28.3690 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.100]; Helo=[xsj-pvapsmtpgw02] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1NAM02HT175 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add clock description for spi-xilinx Signed-off-by: Shubhrajyoti Datta --- .../devicetree/bindings/spi/spi-xilinx.txt | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/spi-xilinx.txt b/Documentation/devicetree/bindings/spi/spi-xilinx.txt index c7b7856..9e683bb 100644 --- a/Documentation/devicetree/bindings/spi/spi-xilinx.txt +++ b/Documentation/devicetree/bindings/spi/spi-xilinx.txt @@ -7,13 +7,16 @@ Required properties: - interrupts : Property with a value describing the interrupt number. - interrupt-parent : Must be core interrupt controller +- clocks: Input clock specifier. Refer to common clock bindings. Optional properties: - xlnx,num-ss-bits : Number of chip selects used. +- clock-names: Input clock name Example: axi_quad_spi@41e00000 { compatible = "xlnx,xps-spi-2.00.a"; + clocks = <&clkc 15>; interrupt-parent = <&intc>; interrupts = <0 31 1>; reg = <0x41e00000 0x10000>;