diff mbox

[RFCv1,1/1] spi: Expand tx_nbits/rx_nbits to add 8-bit transfer

Message ID 1468438477-18883-2-git-send-email-girishm@codeaurora.org (mailing list archive)
State New, archived
Headers show

Commit Message

Girish Mahadevan July 13, 2016, 7:34 p.m. UTC 
Expand the tx_nbits/rx_nbits member of the spi_transfer struct to a 4 bit
value to allow specifying 8 bit transfers (SPI_NBITS_OCTO).

Change-Id: I0b7ab41b2caa8495da431944ccbc0b90942d5dd9
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
---
 include/linux/spi/spi.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

Comments

Mark Brown Aug. 5, 2016, 5:57 p.m. UTC | #1 
On Wed, Jul 13, 2016 at 01:34:37PM -0600, Girish Mahadevan wrote:
> Expand the tx_nbits/rx_nbits member of the spi_transfer struct to a 4 bit
> value to allow specifying 8 bit transfers (SPI_NBITS_OCTO).

Do you have any examples of hardware that might use this on both the
controller and device side?  Hardware like this tends to be memory
mapped rather than driven by a SPI controller in my experience.

> Change-Id: I0b7ab41b2caa8495da431944ccbc0b90942d5dd9

Don't include noise like this in upstream submissions, it means nothing
outside your gerritt install.
diff mbox

Patch

diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 857a9a1..45b958a 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -717,10 +717,11 @@  extern void spi_res_release(struct spi_master *master,
  * by the results of previous messages and where the whole transaction
  * ends when the chipselect goes intactive.
  *
- * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
+ * When SPI can transfer in 1x,2x,4x or 8x. It can get this transfer information
  * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
  * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
- * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
+ * SPI_NBITS_DUAL(2x) SPI_NBITS_QUAD(4x) and SPI_NBITS_OCTO(8x) to support
+ * these four transfers.
  *
  * The code that submits an spi_message (and its spi_transfers)
  * to the lower layers is responsible for managing its memory.
@@ -744,11 +745,12 @@  struct spi_transfer {
 	struct sg_table rx_sg;
 
 	unsigned	cs_change:1;
-	unsigned	tx_nbits:3;
-	unsigned	rx_nbits:3;
+	unsigned	tx_nbits:4;
+	unsigned	rx_nbits:4;
 #define	SPI_NBITS_SINGLE	0x01 /* 1bit transfer */
 #define	SPI_NBITS_DUAL		0x02 /* 2bits transfer */
 #define	SPI_NBITS_QUAD		0x04 /* 4bits transfer */
+#define	SPI_NBITS_OCTO		0x08 /* 4bits transfer */
 	u8		bits_per_word;
 	u16		delay_usecs;
 	u32		speed_hz;