[v4,2/2] fpga: Add support for Lattice iCE40 FPGAs

Message ID	1477776746-3678-2-git-send-email-joel@airwebreathe.org.uk (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-spi-owner@kernel.org> From: Joel Holdsworth <joel@airwebreathe.org.uk> To: atull@opensource.altera.com, moritz.fischer@ettus.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: Joel Holdsworth <joel@airwebreathe.org.uk> Subject: [PATCH v4 2/2] fpga: Add support for Lattice iCE40 FPGAs Date: Sat, 29 Oct 2016 15:32:26 -0600 Message-Id: <1477776746-3678-2-git-send-email-joel@airwebreathe.org.uk> In-Reply-To: <1477776746-3678-1-git-send-email-joel@airwebreathe.org.uk> References: <1477776746-3678-1-git-send-email-joel@airwebreathe.org.uk> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk

diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt new file mode 100644 index 0000000..3d2917c --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt @@ -0,0 +1,23 @@ +Lattice iCE40 FPGA Manager + +Required properties: +- compatible: should contain "lattice,ice40-fpga-mgr" +- reg: SPI chip select +- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) +- cdone-gpio: GPIO connected to CDONE pin +- creset_b-gpio: GPIO connected to CRESET_B pin. Note that CRESET_B is + treated as an active-low output because the signal is + treated as an enable signal, rather than a reset. This + is necessary because the FPGA will enter Master SPI + mode and drive SCK with a clock signal, potentially + jamming other devices on the bus, unless CRESET_B is + held high until the firmware is loaded. + +Example: + ice40: ice40@0 { + compatible = "lattice,ice40-fpga-mgr"; + reg = <0>; + spi-max-frequency = <1000000>; + cdone-gpio = <&gpio 24 GPIO_ACTIVE_HIGH>; + creset_b-gpio = <&gpio 22 GPIO_ACTIVE_LOW>; + }; diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index d614102..85ff429 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -13,6 +13,12 @@ config FPGA if FPGA +config FPGA_MGR_ICE40_SPI + tristate "Lattice iCE40 SPI" + depends on SPI + help + FPGA manager driver support for Lattice iCE40 FPGAs over SPI. + config FPGA_MGR_SOCFPGA tristate "Altera SOCFPGA FPGA Manager" depends on ARCH_SOCFPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 8d83fc6..adb5811 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_FPGA) += fpga-mgr.o # FPGA Manager Drivers +obj-$(CONFIG_FPGA_MGR_ICE40_SPI) += ice40-spi.o obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c new file mode 100644 index 0000000..77ca482 --- /dev/null +++ b/drivers/fpga/ice40-spi.c @@ -0,0 +1,219 @@ +/* + * FPGA Manager Driver for Lattice iCE40. + * + * Copyright (c) 2016 Joel Holdsworth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This driver adds support to the FPGA manager for configuring the SRAM of + * Lattice iCE40 FPGAs through slave SPI. + */ + +#include <linux/fpga/fpga-mgr.h> +#include <linux/gpio/consumer.h> +#include <linux/of_gpio.h> +#include <linux/spi/spi.h> + +#define ICE40_SPI_FPGAMGR_RESET_DELAY 1 /* us (>200ns) */ +#define ICE40_SPI_FPGAMGR_HOUSEKEEPING_DELAY 1200 /* us */ + +#define ICE40_SPI_FPGAMGR_NUM_ACTIVATION_BITS 49 /* bits */ + +struct ice40_fpga_priv { + struct spi_device *dev; + struct gpio_desc *creset_b; + struct gpio_desc *cdone; +}; + +static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr) +{ + struct ice40_fpga_priv *priv = mgr->priv; + return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING : + FPGA_MGR_STATE_UNKNOWN; +} + +static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, u32 flags, + const char *buf, size_t count) +{ + struct ice40_fpga_priv *priv = mgr->priv; + struct spi_device *dev = priv->dev; + struct spi_message message; + int ret; + + if ((flags & FPGA_MGR_PARTIAL_RECONFIG)) { + dev_err(&dev->dev, + "Partial reconfiguration is not supported\n"); + return -ENOTSUPP; + } + + /* Lock the bus, assert CRESET_B and SS_B and delay >200ns */ + ret = spi_bus_lock(dev->master); + if (ret) { + dev_err(&dev->dev, "Failed to lock SPI bus, ret: %d\n", ret); + return ret; + } + + gpiod_set_value(priv->creset_b, 1); + + spi_message_init(&message); + spi_message_add_tail(&(struct spi_transfer){.cs_change = 1, + .delay_usecs = ICE40_SPI_FPGAMGR_RESET_DELAY}, &message); + ret = spi_sync_locked(dev, &message); + if (ret) { + dev_err(&dev->dev, "Failed to set chip-select, ret: %d\n", ret); + spi_bus_unlock(dev->master); + return ret; + } + + /* Come out of reset */ + gpiod_set_value(priv->creset_b, 0); + + /* Check CDONE is de-asserted i.e. the FPGA is reset */ + if (gpiod_get_value(priv->cdone)) { + dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n"); + ret = -EIO; + } + + /* Wait for the housekeeping to complete, and release SS_B */ + spi_message_init(&message); + spi_message_add_tail(&(struct spi_transfer){ + .delay_usecs = ICE40_SPI_FPGAMGR_HOUSEKEEPING_DELAY}, &message); + ret = spi_sync_locked(dev, &message); + if (ret) + dev_err(&dev->dev, "Failed while releasing chip-select, ret: %d\n", ret); + + spi_bus_unlock(dev->master); + + return ret; +} + +static int ice40_fpga_ops_write(struct fpga_manager *mgr, + const char *buf, size_t count) +{ + struct ice40_fpga_priv *priv = mgr->priv; + struct spi_device *dev = priv->dev; + int ret; + + ret = spi_write(dev, buf, count); + if (ret) + dev_err(&dev->dev, "Error sending SPI data, ret: %d\n", ret); + + return ret; +} + +static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr, u32 flags) +{ + struct ice40_fpga_priv *priv = mgr->priv; + struct spi_device *dev = priv->dev; + int ret = 0; + + /* Check CDONE is asserted */ + if (!gpiod_get_value(priv->cdone)) { + dev_err(&dev->dev, + "CDONE was not asserted after firmware transfer\n"); + return -EIO; + } + + /* Send of zero-padding to activate the firmware */ + ret = spi_write(dev, NULL, (ICE40_SPI_FPGAMGR_NUM_ACTIVATION_BITS + + dev->bits_per_word - 1) / dev->bits_per_word); + if (ret) { + dev_err(&dev->dev, "Error sending zero padding, ret: %d\n", + ret); + return ret; + } + + /* Success */ + return 0; +} + +static const struct fpga_manager_ops ice40_fpga_ops = { + .state = ice40_fpga_ops_state, + .write_init = ice40_fpga_ops_write_init, + .write = ice40_fpga_ops_write, + .write_complete = ice40_fpga_ops_write_complete, +}; + +static int ice40_fpga_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct device_node *np = spi->dev.of_node; + struct ice40_fpga_priv *priv; + int ret; + + if (!np) { + dev_err(dev, "No Device Tree entry\n"); + return -EINVAL; + } + + priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = spi; + + /* Check board setup data. */ + if (spi->max_speed_hz > 25000000) { + dev_err(dev, "speed is too high\n"); + return -EINVAL; + } else if (spi->mode & SPI_CPHA) { + dev_err(dev, "bad mode\n"); + return -EINVAL; + } + + /* Set up the GPIOs */ + priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN); + if (IS_ERR(priv->cdone)) { + dev_err(dev, "Failed to get CDONE GPIO: %ld\n", + PTR_ERR(priv->cdone)); + return ret; + } + + priv->creset_b = devm_gpiod_get(dev, "creset_b", GPIOD_OUT_HIGH); + if (IS_ERR(priv->creset_b)) { + dev_err(dev, "Failed to get CRESET_B GPIO: %ld\n", + PTR_ERR(priv->creset_b)); + return ret; + } + + /* Register with the FPGA manager */ + ret = fpga_mgr_register(dev, "Lattice iCE40 FPGA Manager", + &ice40_fpga_ops, priv); + if (ret) { + dev_err(dev, "unable to register FPGA manager"); + return ret; + } + + return 0; +} + +static int ice40_fpga_remove(struct spi_device *spi) +{ + fpga_mgr_unregister(&spi->dev); + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id ice40_fpga_of_match[] = { + { .compatible = "lattice,ice40-fpga-mgr", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ice40_fpga_of_match); +#endif + +static struct spi_driver ice40_fpga_driver = { + .probe = ice40_fpga_probe, + .remove = ice40_fpga_remove, + .driver = { + .name = "ice40spi", + .of_match_table = of_match_ptr(ice40_fpga_of_match), + }, +}; + +module_spi_driver(ice40_fpga_driver); + +MODULE_AUTHOR("Joel Holdsworth <joel@airwebreathe.org.uk>"); +MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager"); +MODULE_LICENSE("GPL v2");

[v4,2/2] fpga: Add support for Lattice iCE40 FPGAs

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