| Message ID | 1482039234-21335-2-git-send-email-joel@airwebreathe.org.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Joel, On Sun, Dec 18, 2016 at 6:33 AM, Joel Holdsworth <joel@airwebreathe.org.uk> wrote: > This adds documentation of the device tree bindings of the Lattice iCE40 > FPGA driver for the FPGA manager framework. > > Signed-off-by: Joel Holdsworth <joel@airwebreathe.org.uk> > Acked-by: Rob Herring <robh@kernel.org> > Acked-by: Alan Tull <atull@opensource.altera.com> > Acked-by: Moritz Fischer <moritz.fischer@ettus.com> > Acked-by: Marek Vasut <marex@denx.de> > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt > @@ -0,0 +1,21 @@ > +Lattice iCE40 FPGA Manager > + > +Required properties: > +- compatible: Should contain "lattice,ice40-fpga-mgr" > +- reg: SPI chip select > +- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) > +- cdone-gpios: GPIO input connected to CDONE pin > +- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note > + that unless the GPIO is held low during startup, the > + FPGA will enter Master SPI mode and drive SCK with a > + clock signal potentially jamming other devices on the > + bus until the firmware is loaded. > + > +Example: > + ice40: ice40@0 { As per ePAPR, node names should be generic names, e.g. "fpga@0". Sorry for not noticing before. > + compatible = "lattice,ice40-fpga-mgr"; > + reg = <0>; > + spi-max-frequency = <1000000>; > + cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; > + reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt new file mode 100644 index 0000000..7e7a78b --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt @@ -0,0 +1,21 @@ +Lattice iCE40 FPGA Manager + +Required properties: +- compatible: Should contain "lattice,ice40-fpga-mgr" +- reg: SPI chip select +- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) +- cdone-gpios: GPIO input connected to CDONE pin +- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note + that unless the GPIO is held low during startup, the + FPGA will enter Master SPI mode and drive SCK with a + clock signal potentially jamming other devices on the + bus until the firmware is loaded. + +Example: + ice40: ice40@0 { + compatible = "lattice,ice40-fpga-mgr"; + reg = <0>; + spi-max-frequency = <1000000>; + cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + };