From patchwork Tue Jun 27 09:45:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 9811201 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 985DA60351 for ; Tue, 27 Jun 2017 09:48:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ACC5328503 for ; Tue, 27 Jun 2017 09:48:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A11A728613; Tue, 27 Jun 2017 09:48:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2FE0B28503 for ; Tue, 27 Jun 2017 09:48:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752884AbdF0Jry (ORCPT ); Tue, 27 Jun 2017 05:47:54 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:51860 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752796AbdF0Jqd (ORCPT ); Tue, 27 Jun 2017 05:46:33 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D4C72607E2; Tue, 27 Jun 2017 09:46:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498556777; bh=tD0w5JTmBP0XvP9ubgkVT5anjnvsulR3TKWsEPn7UgI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aOEKb5HL4FoW9/L0A2iZH8rOMa3l6gSgPyNeMHtm9RXO3aDSoWOltxmVu/Ft82wY7 y/ygbroMjsOq3T/xdXwwovdt6NsP18WxDOJ/XFzHWYgBFPzX7ZTdvR5ht6O01vJg4C NTpMpkQl8iek68hVt3pdhx11ntijsGaX5Bbeh6UU= Received: from varda-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: varada@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 89EE3607E2; Tue, 27 Jun 2017 09:46:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1498556777; bh=tD0w5JTmBP0XvP9ubgkVT5anjnvsulR3TKWsEPn7UgI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aOEKb5HL4FoW9/L0A2iZH8rOMa3l6gSgPyNeMHtm9RXO3aDSoWOltxmVu/Ft82wY7 y/ygbroMjsOq3T/xdXwwovdt6NsP18WxDOJ/XFzHWYgBFPzX7ZTdvR5ht6O01vJg4C NTpMpkQl8iek68hVt3pdhx11ntijsGaX5Bbeh6UU= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 89EE3607E2 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=varada@codeaurora.org From: Varadarajan Narayanan To: broonie@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org Cc: Varadarajan Narayanan , Matthew McClintock Subject: [PATCH v4 09/14] spi: qup: refactor spi_qup_io_config into two functions Date: Tue, 27 Jun 2017 15:15:26 +0530 Message-Id: <1498556731-13087-10-git-send-email-varada@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498556731-13087-1-git-send-email-varada@codeaurora.org> References: <1498556731-13087-1-git-send-email-varada@codeaurora.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is in preparation for handling transactions larger than 64K-1 bytes in block mode, which is currently unsupported and quietly fails. We need to break these into two functions 1) prep is called once per spi_message and 2) io_config is called once per spi-qup bus transaction This is just refactoring, there should be no functional change Signed-off-by: Matthew McClintock Signed-off-by: Varadarajan Narayanan --- drivers/spi/spi-qup.c | 109 +++++++++++++++++++++++++++++++------------------- 1 file changed, 67 insertions(+), 42 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 1a83248..bfb6d27 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -543,12 +543,11 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id) return IRQ_HANDLED; } -/* set clock freq ... bits per word */ -static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) +/* set clock freq ... bits per word, determine mode */ +static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer) { struct spi_qup *controller = spi_master_get_devdata(spi->master); - u32 config, iomode, control; - int ret, n_words; + int ret; if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { dev_err(controller->dev, "too big size for loopback %d > %d\n", @@ -563,32 +562,59 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) return -EIO; } - if (spi_qup_set_state(controller, QUP_STATE_RESET)) { - dev_err(controller->dev, "cannot set RESET state\n"); - return -EIO; - } - controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); controller->n_words = xfer->len / controller->w_size; - n_words = controller->n_words; - - if (n_words <= (controller->in_fifo_sz / sizeof(u32))) { + if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) controller->mode = QUP_IO_M_MODE_FIFO; + else if (spi->master->can_dma && + spi->master->can_dma(spi->master, spi, xfer) && + spi->master->cur_msg_mapped) + controller->mode = QUP_IO_M_MODE_BAM; + else + controller->mode = QUP_IO_M_MODE_BLOCK; + + return 0; +} + +/* prep qup for another spi transaction of specific type */ +static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) +{ + struct spi_qup *controller = spi_master_get_devdata(spi->master); + u32 config, iomode, control; + unsigned long flags; + + spin_lock_irqsave(&controller->lock, flags); + controller->xfer = xfer; + controller->error = 0; + controller->rx_bytes = 0; + controller->tx_bytes = 0; + spin_unlock_irqrestore(&controller->lock, flags); + + + if (spi_qup_set_state(controller, QUP_STATE_RESET)) { + dev_err(controller->dev, "cannot set RESET state\n"); + return -EIO; + } - writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT); - writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT); + switch (controller->mode) { + case QUP_IO_M_MODE_FIFO: + reinit_completion(&controller->done); + writel_relaxed(controller->n_words, + controller->base + QUP_MX_READ_CNT); + writel_relaxed(controller->n_words, + controller->base + QUP_MX_WRITE_CNT); /* must be zero for FIFO */ writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); - } else if (spi->master->can_dma && - spi->master->can_dma(spi->master, spi, xfer) && - spi->master->cur_msg_mapped) { - - controller->mode = QUP_IO_M_MODE_BAM; - - writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); - writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); + break; + case QUP_IO_M_MODE_BAM: + reinit_completion(&controller->txc); + reinit_completion(&controller->rxc); + writel_relaxed(controller->n_words, + controller->base + QUP_MX_INPUT_CNT); + writel_relaxed(controller->n_words, + controller->base + QUP_MX_OUTPUT_CNT); /* must be zero for BLOCK and BAM */ writel_relaxed(0, controller->base + QUP_MX_READ_CNT); writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); @@ -606,19 +632,25 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer) if (xfer->tx_buf) writel_relaxed(0, input_cnt); else - writel_relaxed(n_words, input_cnt); + writel_relaxed(controller->n_words, input_cnt); writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); } - } else { - - controller->mode = QUP_IO_M_MODE_BLOCK; - - writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT); - writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT); + break; + case QUP_IO_M_MODE_BLOCK: + reinit_completion(&controller->done); + writel_relaxed(controller->n_words, + controller->base + QUP_MX_INPUT_CNT); + writel_relaxed(controller->n_words, + controller->base + QUP_MX_OUTPUT_CNT); /* must be zero for BLOCK and BAM */ writel_relaxed(0, controller->base + QUP_MX_READ_CNT); writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); + break; + default: + dev_err(controller->dev, "unknown mode = %d\n", + controller->mode); + return -EIO; } iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); @@ -707,6 +739,10 @@ static int spi_qup_transfer_one(struct spi_master *master, unsigned long timeout, flags; int ret = -EIO; + ret = spi_qup_io_prep(spi, xfer); + if (ret) + return ret; + ret = spi_qup_io_config(spi, xfer); if (ret) return ret; @@ -715,21 +751,10 @@ static int spi_qup_transfer_one(struct spi_master *master, timeout = DIV_ROUND_UP(xfer->len * 8, timeout); timeout = 100 * msecs_to_jiffies(timeout); - spin_lock_irqsave(&controller->lock, flags); - controller->xfer = xfer; - controller->error = 0; - controller->rx_bytes = 0; - controller->tx_bytes = 0; - spin_unlock_irqrestore(&controller->lock, flags); - - if (spi_qup_is_dma_xfer(controller->mode)) { - reinit_completion(&controller->rxc); - reinit_completion(&controller->txc); + if (spi_qup_is_dma_xfer(controller->mode)) ret = spi_qup_do_dma(master, xfer, timeout); - } else { - reinit_completion(&controller->done); + else ret = spi_qup_do_pio(master, xfer, timeout); - } if (ret) goto exit;