From patchwork Mon Sep 17 07:16:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mason Yang X-Patchwork-Id: 10602155 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9187A14DA for ; Mon, 17 Sep 2018 07:41:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 836C329660 for ; Mon, 17 Sep 2018 07:41:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7784429649; Mon, 17 Sep 2018 07:41:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1849C2962D for ; Mon, 17 Sep 2018 07:41:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728495AbeIQNHR (ORCPT ); Mon, 17 Sep 2018 09:07:17 -0400 Received: from twhmllg3.macronix.com ([211.75.127.131]:42634 "EHLO TWHMLLG3.macronix.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727491AbeIQNHR (ORCPT ); Mon, 17 Sep 2018 09:07:17 -0400 Received: from TWHMLLG3.macronix.com (localhost [127.0.0.2] (may be forged)) by TWHMLLG3.macronix.com with ESMTP id w8H7HEjC079006 for ; Mon, 17 Sep 2018 15:17:14 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) Received: from localhost.localdomain ([172.17.195.96]) by TWHMLLG3.macronix.com with ESMTP id w8H7GmMb078541; Mon, 17 Sep 2018 15:16:51 +0800 (GMT-8) (envelope-from masonccyang@mxic.com.tw) From: masonccyang@mxic.com.tw To: broonie@kernel.org, tpiepho@impinj.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Cc: boris.brezillon@bootlin.com, juliensu@mxic.com.tw, zhengxunli@mxic.com.tw, masonccyang@mxic.com.tw Subject: [PATCH 2/2] dt-binding: spi: Document Macronix controller bindings Date: Mon, 17 Sep 2018 15:16:19 +0800 Message-Id: <1537168579-31593-3-git-send-email-masonccyang@mxic.com.tw> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1537168579-31593-1-git-send-email-masonccyang@mxic.com.tw> References: <1537168579-31593-1-git-send-email-masonccyang@mxic.com.tw> X-MAIL: TWHMLLG3.macronix.com w8H7GmMb078541 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Mason Yang Document the bindings used by the Macronix controller. Signed-off-by: Mason Yang --- Documentation/devicetree/bindings/spi/spi-mxic.txt | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-mxic.txt diff --git a/Documentation/devicetree/bindings/spi/spi-mxic.txt b/Documentation/devicetree/bindings/spi/spi-mxic.txt new file mode 100644 index 0000000..529f2da --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-mxic.txt @@ -0,0 +1,34 @@ +Macronix SPI controller Device Tree Bindings +-------------------------------------------- + +Required properties: +- compatible: should be "mxicy,mx25f0a-spi" +- #address-cells: should be 1 +- #size-cells: should be 0 +- reg: should contain 2 entries, one for the registers and one for the direct + mapping area +- reg-names: should contain "regs" and "dirmap" +- interrupts: interrupt line connected to the SPI controller +- clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk" +- clocks: should contain 3 entries for the "ps_clk", "send_clk" and + "send_dly_clk" clocks + +Example: + + spi@43c30000 { + compatible = "mxicy,mx25f0a-spi"; + reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>; + reg-names = "regs", "dirmap"; + clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>; + clock-names = "send_clk", "send_dly_clk", "ps_clk"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + };