@@ -764,6 +764,11 @@ static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
else
command1 &= ~SPI_LSBIT_FE;
+ if (spi->mode & SPI_LSBYTE_FIRST)
+ command1 |= SPI_LSBYTE_FE;
+ else
+ command1 &= ~SPI_LSBYTE_FE;
+
if (spi->mode & SPI_3WIRE)
command1 |= SPI_BIDIROE;
else
@@ -1200,7 +1205,8 @@ static int tegra_spi_probe(struct platform_device *pdev)
/* the spi->mode bits understood by this driver: */
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
- SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
+ SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE |
+ SPI_LSBYTE_FIRST;
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
master->setup = tegra_spi_setup;
master->transfer_one_message = tegra_spi_transfer_one_message;
Tegra SPI master controller supports configuring least significant first byte order or most significant first byte order for transfers. This patch adds SPI_LSBYTE_FIRST to supported mode list and also configures byte order based on the mode request for transfer. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/spi/spi-tegra114.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)