From patchwork Mon Nov 18 04:57:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: luhua xu X-Patchwork-Id: 11248859 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5068314E5 for ; Mon, 18 Nov 2019 04:58:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 293BC2071C for ; Mon, 18 Nov 2019 04:58:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="c6hqaBV7" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726347AbfKRE6S (ORCPT ); Sun, 17 Nov 2019 23:58:18 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:42192 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726314AbfKRE6S (ORCPT ); Sun, 17 Nov 2019 23:58:18 -0500 X-UUID: a73adb0b35aa410785b12fa22b005973-20191118 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=UHP1TLO/xSCKu2mOHO9OAMb60Y2rR1gXwyO+sDfrAaA=; b=c6hqaBV7JLWC4660XgazL+JWbzP67gEOP1k/tGFMf5PSfR+jmb+A96ufMxT/PcPAcyab1UsydpWMmiPn0O8cmoqp2OFkwITbrDAusx6GPOSLtsue7rCb+3C97adYyTiFWzOw8LXKiUuQy7v8hWIfL7GwGw4wolUE4G10owYuxhI=; X-UUID: a73adb0b35aa410785b12fa22b005973-20191118 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1066876529; Mon, 18 Nov 2019 12:58:05 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 18 Nov 2019 12:58:01 +0800 Received: from localhost.localdomain (10.15.20.246) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 18 Nov 2019 12:57:52 +0800 From: Luhua Xu To: Mark Brown , Matthias Brugger , Allison Randal , Enrico Weigelt , Kate Stewart , Leilk Liu , Thomas Gleixner CC: , , , , Luhua Xu Subject: [PATCH 2/2] spi: mediatek: add cs timing configuration support Date: Mon, 18 Nov 2019 12:57:17 +0800 Message-ID: <1574053037-26721-3-git-send-email-luhua.xu@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1574053037-26721-1-git-send-email-luhua.xu@mediatek.com> References: <1574053037-26721-1-git-send-email-luhua.xu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 626524C0662AC8EB3D01DB687214712F64B2E88F0CAD8E749B2E550F40EB27E92000:8 X-MTK: N Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add configure SPI CS setup/hold/idle delays in terms of clk count support, and use one period of current spi speed as default if setup/hold/idle not indicated. Signed-off-by: Luhua Xu --- drivers/spi/spi-mt65xx.c | 41 +++++++++++++++++++++++++------- include/linux/platform_data/spi-mt65xx.h | 5 ++++ 2 files changed, 37 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index f599cce..98df9d1 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -140,6 +140,9 @@ static const struct mtk_spi_compatible mt8183_compat = { */ static const struct mtk_chip_config mtk_default_chip_info = { .sample_sel = 0, + .setup_cnt = 0, + .hold_cnt = 0, + .idle_cnt = 0, }; static const struct of_device_id mtk_spi_of_match[] = { @@ -281,10 +284,13 @@ static void mtk_spi_set_cs(struct spi_device *spi, bool enable) } static void mtk_spi_prepare_transfer(struct spi_master *master, - struct spi_transfer *xfer) + struct spi_transfer *xfer, + struct spi_device *spi) { u32 spi_clk_hz, div, sck_time, cs_time, reg_val = 0; struct mtk_spi *mdata = spi_master_get_devdata(master); + struct mtk_chip_config *chip_config = spi->controller_data; + u32 cs_setup, cs_hold, cs_idle; spi_clk_hz = clk_get_rate(mdata->spi_clk); if (xfer->speed_hz < spi_clk_hz / 2) @@ -295,29 +301,46 @@ static void mtk_spi_prepare_transfer(struct spi_master *master, sck_time = (div + 1) / 2; cs_time = sck_time * 2; + if (chip_config->setup_cnt) + cs_setup = chip_config->setup_cnt; + else + cs_setup = cs_time; + + if (chip_config->hold_cnt) + cs_hold = chip_config->hold_cnt; + else + cs_hold = cs_time; + + if (chip_config->idle_cnt) + cs_idle = chip_config->idle_cnt; + else + cs_idle = cs_time; + if (mdata->dev_comp->enhance_timing) { - reg_val |= (((sck_time - 1) & 0xffff) + reg_val = (((sck_time - 1) & 0xffff) << SPI_CFG0_SCK_HIGH_OFFSET); reg_val |= (((sck_time - 1) & 0xffff) << SPI_ADJUST_CFG0_SCK_LOW_OFFSET); writel(reg_val, mdata->base + SPI_CFG2_REG); - reg_val |= (((cs_time - 1) & 0xffff) + + reg_val = (((cs_hold - 1) & 0xffff) << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); - reg_val |= (((cs_time - 1) & 0xffff) + reg_val |= (((cs_setup - 1) & 0xffff) << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); writel(reg_val, mdata->base + SPI_CFG0_REG); } else { reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_HIGH_OFFSET); reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); - reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); - reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); + reg_val |= (((cs_hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); + reg_val |= (((cs_setup - 1) & 0xff) + << SPI_CFG0_CS_SETUP_OFFSET); writel(reg_val, mdata->base + SPI_CFG0_REG); } reg_val = readl(mdata->base + SPI_CFG1_REG); reg_val &= ~SPI_CFG1_CS_IDLE_MASK; - reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); + reg_val |= (((cs_idle - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); writel(reg_val, mdata->base + SPI_CFG1_REG); } @@ -426,7 +449,7 @@ static int mtk_spi_fifo_transfer(struct spi_master *master, mdata->cur_transfer = xfer; mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); mdata->num_xfered = 0; - mtk_spi_prepare_transfer(master, xfer); + mtk_spi_prepare_transfer(master, xfer, spi); mtk_spi_setup_packet(master); cnt = xfer->len / 4; @@ -458,7 +481,7 @@ static int mtk_spi_dma_transfer(struct spi_master *master, mdata->cur_transfer = xfer; mdata->num_xfered = 0; - mtk_spi_prepare_transfer(master, xfer); + mtk_spi_prepare_transfer(master, xfer, spi); cmd = readl(mdata->base + SPI_CMD_REG); if (xfer->tx_buf) diff --git a/include/linux/platform_data/spi-mt65xx.h b/include/linux/platform_data/spi-mt65xx.h index 65fd5ffd2..80d280e 100644 --- a/include/linux/platform_data/spi-mt65xx.h +++ b/include/linux/platform_data/spi-mt65xx.h @@ -12,5 +12,10 @@ /* Board specific platform_data */ struct mtk_chip_config { u32 sample_sel; + + /* CS timing configuration in terms of clock count */ + u16 setup_cnt; + u16 hold_cnt; + u8 idle_cnt; }; #endif