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[3/6] dt-bindings: snps,dw-apb-ssi: Add compatible string for DesignWare DWC_ssi

Message ID 1575907443-26377-4-git-send-email-wan.ahmad.zainie.wan.mohamad@intel.com (mailing list archive)
State New, archived
Headers show
Series spi: dw: Add support for DesignWare DWC_ssi | expand

Commit Message

Wan Ahmad Zainie Dec. 9, 2019, 4:04 p.m. UTC 
From: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>

This patch adds compatible string "snps,dwc-ssi-1.01a" to the above DT
binding document, to provide support for DesignWare DWC_ssi IP [1].

Current driver supports DW_apb_ssi IP [2].

References:
[1] https://www.synopsys.com/dw/ipdir.php?c=dwc_ssi
[2] https://www.synopsys.com/dw/ipdir.php?c=DW_apb_ssi

Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 59904bdbef66..fccd4b0f91f5 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -6,6 +6,7 @@  Required properties:
   - "snps,dw-apb-ssi"
   - "mscc,<soc>-spi", where soc is "ocelot" or "jaguar2"
   - "amazon,alpine-dw-apb-ssi"
+  - "snps,dwc-ssi-1.01a"
 
 - reg : The register base for the controller. For "mscc,<soc>-spi", a second
   register set is required (named ICPU_CFG:SPI_MST)