From patchwork Mon May 25 03:40:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dillon Min X-Patchwork-Id: 11567951 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0274A15E4 for ; Mon, 25 May 2020 03:41:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DFF9720849 for ; Mon, 25 May 2020 03:41:39 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="b9x/beh8" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388817AbgEYDlf (ORCPT ); Sun, 24 May 2020 23:41:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388397AbgEYDle (ORCPT ); Sun, 24 May 2020 23:41:34 -0400 Received: from mail-pj1-x1044.google.com (mail-pj1-x1044.google.com [IPv6:2607:f8b0:4864:20::1044]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB39DC061A0E; Sun, 24 May 2020 20:41:34 -0700 (PDT) Received: by mail-pj1-x1044.google.com with SMTP id a5so8001011pjh.2; Sun, 24 May 2020 20:41:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JHR9IFaRgCyJGWikuHqyC0B14pMQIGmyd5Kpq3MNpmQ=; b=b9x/beh8V8+Wi3TKqrBgqD2YLsbTxg11tUo1GMv4hQuU9CXkFipOzeKKw1ZhH558DJ r3oDIli3++aJuKFgOZhAMmIPgFHizDXljnjeuUsvEF9PQy3XdYGIYSNIkKY+vG+nZnUC S17nYhtoQLypMlGwlOfC4yczd2ZcZeMhwYt5FPiTVMn0/n7muwoxYy7K5NrlRNkjOZoA uYMMg1PRq7PQOTUKTlhGadlAru4Ngw2QUZcJmDsrxr/wcYKPqhI3yGp1of9jxHDiSs73 YsOHksI+ec5abVm67ec+Wz5N7W8PH9R8LQQhLaETnupDLM+bilLEXZ1lUOV5xhLPeWvu MVZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JHR9IFaRgCyJGWikuHqyC0B14pMQIGmyd5Kpq3MNpmQ=; b=ik63Rp4BM14AEMUmUEdJnlgPR60BGGMcy4iH6/QL7XyyCDoaa4yFN0v5PFyqfrHgJ8 YtN/1FAUfP8IQq/SakoweFGPm6WG8R4n/DvRGokzViARXdDHlg4qQ8BGI8ATUy4HRpfx n1iL74SdC8FIrJOo9fx1POK0b8HPnKAYlnr0+ZkSWWTOFBhDqHh5qhJMYh5ZaezSE0Lw I2Wzx4udOrqT3v3/ibykAbKyO9pNSE+yUOC7qD9TB0ZdUsKR0WXB2oKqFsi/85T+b8j4 maDabiCQOyI5HPabhLgcQ0/mxWQBsOx85UbHRgqXwOwmUud8qnXjNEyWNru+6pWkb99h ZteQ== X-Gm-Message-State: AOAM5335Bo6hNYqQFF7d3+lIKku3qsOW61AJcFC6EfGVDGaX+SD4Jnz+ /JN5exLuse/RBl/g4xrVQFI= X-Google-Smtp-Source: ABdhPJwFd19cwDs3kghDA6cyFKAQQDyzxswSNn1g5n0asibuokVH+325D0MWIcoam+IOMZD80TfYMg== X-Received: by 2002:a17:902:bc82:: with SMTP id bb2mr5540650plb.107.1590378094241; Sun, 24 May 2020 20:41:34 -0700 (PDT) Received: from fmin-OptiPlex-7060.nreal.work ([103.206.191.44]) by smtp.gmail.com with ESMTPSA id 7sm11981695pfc.203.2020.05.24.20.41.29 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 24 May 2020 20:41:33 -0700 (PDT) From: dillon.minfei@gmail.com To: robh+dt@kernel.org, p.zabel@pengutronix.de, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, thierry.reding@gmail.com, sam@ravnborg.org, airlied@linux.ie, daniel@ffwll.ch, mturquette@baylibre.com, sboyd@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, dri-devel@lists.freedesktop.org, linux-clk@vger.kernel.org, dillon min Subject: [PATCH v5 5/8] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate, fix duplicated ltdc clock register to 'clk_core' case ltdc's clock turn off by clk_disable_unused() Date: Mon, 25 May 2020 11:40:59 +0800 Message-Id: <1590378062-7965-6-git-send-email-dillon.minfei@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1590378062-7965-1-git-send-email-dillon.minfei@gmail.com> References: <1590378062-7965-1-git-send-email-dillon.minfei@gmail.com> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: dillon min ltdc set clock rate crashed 'post_div_data[]''s pll_num is PLL_I2S, PLL_SAI (number is 1,2). but, as pll_num is offset of 'clks[]' input to clk_register_pll_div(), which is FCLK, CLK_LSI, defined in 'include/dt-bindings/clock/stm32fx-clock.h' so, this is a null object at the register time. then, in ltdc's clock is_enabled(), enable(), will call to_clk_gate(). will return a null object, cause kernel crashed. need change pll_num to PLL_VCO_I2S, PLL_VCO_SAI for 'post_div_data[]' duplicated ltdc clock 'stm32f429_gates[]' has a member 'ltdc' register to 'clk_core', but no upper driver use it, ltdc driver use the lcd-tft defined in 'stm32f429_aux_clk[]'. after system startup, as stm32f429_gates[]'s ltdc enable_count is zero, so turn off by clk_disable_unused() Changes since V3: 1 drop last wrong changes about 'CLK_IGNORE_UNUSED' patch 2 fix PLL_SAI mismatch with PLL_VCO_SAI Signed-off-by: dillon min --- drivers/clk/clk-stm32f4.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c index 18117ce..fa62e99 100644 --- a/drivers/clk/clk-stm32f4.c +++ b/drivers/clk/clk-stm32f4.c @@ -129,7 +129,6 @@ static const struct stm32f4_gate_data stm32f429_gates[] __initconst = { { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" }, { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" }, { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" }, - { STM32F4_RCC_APB2ENR, 26, "ltdc", "apb2_div" }, }; static const struct stm32f4_gate_data stm32f469_gates[] __initconst = { @@ -557,13 +556,13 @@ static const struct clk_div_table post_divr_table[] = { #define MAX_POST_DIV 3 static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = { - { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q", + { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL}, - { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q", + { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL }, - { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, + { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table }, };