From patchwork Fri Feb 5 18:59:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alain Volmat X-Patchwork-Id: 12070785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A456C433E0 for ; Fri, 5 Feb 2021 19:06:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D365B64E33 for ; Fri, 5 Feb 2021 19:06:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232679AbhBERXF (ORCPT ); Fri, 5 Feb 2021 12:23:05 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:9622 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233722AbhBERSa (ORCPT ); Fri, 5 Feb 2021 12:18:30 -0500 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 115IrH08027369; Fri, 5 Feb 2021 19:59:47 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=selector1; bh=xRI47dfOA+De66iyWb2pGiRIORaw5rau1QhvuvTsAXw=; b=oG/zCSLWKZeSm7jL8sZKfDyGN9eDj2cH45e8G/vP7TpjzS5hp6h4A24DZ5DkRBPcSuQr uVT5XWv+mYEIMFbR8E/K3uOR3mZ4IUZ//GrRM25EbUxmo4xramxjEbdkRuXJAxorRUAr AYmUUtOzjOikoejb6E7fYl8ctkpnidQKWuI1xNOqMGmX7+hg0Go7OM199GgRH9MissbE zz1axVF3HKfpoJ/Sdits7tlMNCXXpHmfk3pHuX9NeekjvyPn7up8AH+l4oxT5sGQSc5N 6r6cP2TXUffdjM2lessbeKDBw10gn82YDc3yNew5DSeHvtCb4mDtaHfgOrfJMYp2ELe4 Kw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 36d0nshe3n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 05 Feb 2021 19:59:47 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 902C9100034; Fri, 5 Feb 2021 19:59:46 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag2node3.st.com [10.75.127.6]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 80CB12C38D3; Fri, 5 Feb 2021 19:59:46 +0100 (CET) Received: from localhost (10.75.127.47) by SFHDAG2NODE3.st.com (10.75.127.6) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 5 Feb 2021 19:59:46 +0100 From: Alain Volmat To: , CC: , , , , , , , Subject: [PATCH v2 3/8] spi: stm32: use bitfield macros Date: Fri, 5 Feb 2021 19:59:27 +0100 Message-ID: <1612551572-495-4-git-send-email-alain.volmat@foss.st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612551572-495-1-git-send-email-alain.volmat@foss.st.com> References: <1612551572-495-1-git-send-email-alain.volmat@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG2NODE3.st.com (10.75.127.6) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.737 definitions=2021-02-05_10:2021-02-05,2021-02-05 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Amelie Delaunay To avoid defining shift and mask separately and hand-coding the bit manipulation, use the bitfield macros. Signed-off-by: Amelie Delaunay Signed-off-by: Alain Volmat --- v2: reordered within the serie drivers/spi/spi-stm32.c | 54 ++++++++++++++--------------------------- 1 file changed, 18 insertions(+), 36 deletions(-) diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index 2b4ea4cba00b..a46132e81533 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -5,6 +5,7 @@ // Copyright (C) 2017, STMicroelectronics - All Rights Reserved // Author(s): Amelie Delaunay for STMicroelectronics. +#include #include #include #include @@ -94,27 +95,22 @@ #define STM32H7_SPI_CR1_SSI BIT(12) /* STM32H7_SPI_CR2 bit fields */ -#define STM32H7_SPI_CR2_TSIZE_SHIFT 0 #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0) +#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0) /* STM32H7_SPI_CFG1 bit fields */ -#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0 #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0) -#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5 #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5) #define STM32H7_SPI_CFG1_RXDMAEN BIT(14) #define STM32H7_SPI_CFG1_TXDMAEN BIT(15) -#define STM32H7_SPI_CFG1_MBR_SHIFT 28 #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28) +#define STM32H7_SPI_CFG1_MBR_SHIFT 28 #define STM32H7_SPI_CFG1_MBR_MIN 0 #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) /* STM32H7_SPI_CFG2 bit fields */ -#define STM32H7_SPI_CFG2_MIDI_SHIFT 4 #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4) -#define STM32H7_SPI_CFG2_COMM_SHIFT 17 #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17) -#define STM32H7_SPI_CFG2_SP_SHIFT 19 #define STM32H7_SPI_CFG2_SP GENMASK(21, 19) #define STM32H7_SPI_CFG2_MASTER BIT(22) #define STM32H7_SPI_CFG2_LSBFRST BIT(23) @@ -140,7 +136,6 @@ #define STM32H7_SPI_SR_OVR BIT(6) #define STM32H7_SPI_SR_MODF BIT(9) #define STM32H7_SPI_SR_SUSP BIT(11) -#define STM32H7_SPI_SR_RXPLVL_SHIFT 13 #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13) #define STM32H7_SPI_SR_RXWNE BIT(15) @@ -417,9 +412,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); - max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >> - STM32H7_SPI_CFG1_DSIZE_SHIFT; - max_bpw += 1; + max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1; spin_unlock_irqrestore(&spi->lock, flags); @@ -587,8 +580,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi) static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) { u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); - u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> - STM32H7_SPI_SR_RXPLVL_SHIFT; + u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr); while ((spi->rx_len > 0) && ((sr & STM32H7_SPI_SR_RXP) || @@ -615,8 +607,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) } sr = readl_relaxed(spi->base + STM32H7_SPI_SR); - rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> - STM32H7_SPI_SR_RXPLVL_SHIFT; + rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr); } dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, @@ -1385,15 +1376,13 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi) bpw = spi->cur_bpw - 1; cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE; - cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) & - STM32H7_SPI_CFG1_DSIZE; + cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw); spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); fthlv = spi->cur_fthlv - 1; cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV; - cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) & - STM32H7_SPI_CFG1_FTHLV; + cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv); writel_relaxed( (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & @@ -1411,8 +1400,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) u32 clrb = 0, setb = 0; clrb |= spi->cfg->regs->br.mask; - setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) & - spi->cfg->regs->br.mask; + setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask; writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & ~clrb) | setb, @@ -1503,8 +1491,7 @@ static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) } cfg2_clrb |= STM32H7_SPI_CFG2_COMM; - cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) & - STM32H7_SPI_CFG2_COMM; + cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_COMM, mode); writel_relaxed( (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & @@ -1527,14 +1514,15 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) cfg2_clrb |= STM32H7_SPI_CFG2_MIDI; if ((len > 1) && (spi->cur_midi > 0)) { u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); - u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), - (u32)STM32H7_SPI_CFG2_MIDI >> - STM32H7_SPI_CFG2_MIDI_SHIFT); + u32 midi = min_t(u32, + DIV_ROUND_UP(spi->cur_midi, sck_period_ns), + FIELD_GET(STM32H7_SPI_CFG2_MIDI, + STM32H7_SPI_CFG2_MIDI)); + dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", sck_period_ns, midi, midi * sck_period_ns); - cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) & - STM32H7_SPI_CFG2_MIDI; + cfg2_setb |= FIELD_PREP(STM32H7_SPI_CFG2_MIDI, midi); } writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & @@ -1549,14 +1537,8 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) */ static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) { - u32 cr2_clrb = 0, cr2_setb = 0; - - if (nb_words <= (STM32H7_SPI_CR2_TSIZE >> - STM32H7_SPI_CR2_TSIZE_SHIFT)) { - cr2_clrb |= STM32H7_SPI_CR2_TSIZE; - cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT; - writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) & - ~cr2_clrb) | cr2_setb, + if (nb_words <= STM32H7_SPI_TSIZE_MAX) { + writel_relaxed(FIELD_PREP(STM32H7_SPI_CR2_TSIZE, nb_words), spi->base + STM32H7_SPI_CR2); } else { return -EMSGSIZE;