From patchwork Tue Oct 1 20:14:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trent Piepho X-Patchwork-Id: 2971851 Return-Path: X-Original-To: patchwork-spi-devel-general@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3E79D9F527 for ; Tue, 1 Oct 2013 20:14:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 71362203DF for ; Tue, 1 Oct 2013 20:14:46 +0000 (UTC) Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 74451201C4 for ; Tue, 1 Oct 2013 20:14:45 +0000 (UTC) Received: from localhost ([127.0.0.1] helo=sfs-ml-1.v29.ch3.sourceforge.com) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1VR6LE-0005Lb-SF; Tue, 01 Oct 2013 20:14:44 +0000 Received: from sog-mx-3.v43.ch3.sourceforge.com ([172.29.43.193] helo=mx.sourceforge.net) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1VR6LD-0005LM-5o for spi-devel-general@lists.sourceforge.net; Tue, 01 Oct 2013 20:14:43 +0000 Received-SPF: pass (sog-mx-3.v43.ch3.sourceforge.com: domain of gmail.com designates 209.85.160.51 as permitted sender) client-ip=209.85.160.51; envelope-from=tpiepho@gmail.com; helo=mail-pb0-f51.google.com; Received: from mail-pb0-f51.google.com ([209.85.160.51]) by sog-mx-3.v43.ch3.sourceforge.com with esmtps (TLSv1:RC4-SHA:128) (Exim 4.76) id 1VR6L4-0000Bb-4d for spi-devel-general@lists.sourceforge.net; Tue, 01 Oct 2013 20:14:43 +0000 Received: by mail-pb0-f51.google.com with SMTP id jt11so7586963pbb.24 for ; Tue, 01 Oct 2013 13:14:28 -0700 (PDT) X-Received: by 10.66.142.193 with SMTP id ry1mr10905851pab.150.1380658468236; Tue, 01 Oct 2013 13:14:28 -0700 (PDT) Received: from [127.0.1.1] (174-31-223-101.tukw.qwest.net. [174.31.223.101]) by mx.google.com with ESMTPSA id rv9sm8598664pbc.4.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 01 Oct 2013 13:14:27 -0700 (PDT) Subject: [PATCH 02/13] spi: spi-mxs: Remove mxs_spi_enable and mxs_spi_disable To: spi-devel-general@lists.sourceforge.net, Mark Brown From: Trent Piepho Date: Tue, 01 Oct 2013 13:14:32 -0700 Message-ID: <20131001201432.13660.6230.stgit@Graphine> In-Reply-To: <20131001201425.13660.72740.stgit@Graphine> References: <20131001201425.13660.72740.stgit@Graphine> User-Agent: StGit/0.15 MIME-Version: 1.0 X-Spam-Score: -1.6 (-) X-Headers-End: 1VR6L4-0000Bb-4d Cc: Marek Vasut , Fabio Estevam , Shawn Guo X-BeenThere: spi-devel-general@lists.sourceforge.net X-Mailman-Version: 2.1.9 Precedence: list List-Id: Linux SPI core/device drivers discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: spi-devel-general-bounces@lists.sourceforge.net X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM,RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP These functions consist of nothing but one single writel call and are only called once. And the names really aren't accurate or clear, since they don't enable or disble SPI. Rather they set the bit that controls the state of CS at the end of transfer. It easier to follow the code to just set this bit with a writel() along with all the other bits being set in the same function. Signed-off-by: Trent Piepho Cc: Marek Vasut Cc: Fabio Estevam Cc: Shawn Guo --- drivers/spi/spi-mxs.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) ------------------------------------------------------------------------------ October Webinars: Code for Performance Free Intel webinars can help you accelerate application performance. Explore tips for MPI, OpenMP, advanced profiling, and more. Get the most from the latest Intel processors and coprocessors. See abstracts and register > http://pubads.g.doubleclick.net/gampad/clk?id=60134791&iu=/4140/ostg.clktrk diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index e6172ae..991ee01 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c @@ -145,22 +145,6 @@ static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs) writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); } -static inline void mxs_spi_enable(struct mxs_spi *spi) -{ - struct mxs_ssp *ssp = &spi->ssp; - - writel(BM_SSP_CTRL0_IGNORE_CRC, - ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); -} - -static inline void mxs_spi_disable(struct mxs_spi *spi) -{ - struct mxs_ssp *ssp = &spi->ssp; - - writel(BM_SSP_CTRL0_IGNORE_CRC, - ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); -} - static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set) { const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT); @@ -335,13 +319,15 @@ static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs, struct mxs_ssp *ssp = &spi->ssp; if (*first) - mxs_spi_enable(spi); + writel(BM_SSP_CTRL0_IGNORE_CRC, + ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR); mxs_spi_set_cs(spi, cs); while (len--) { if (*last && len == 0) - mxs_spi_disable(spi); + writel(BM_SSP_CTRL0_IGNORE_CRC, + ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET); if (ssp->devid == IMX23_SSP) { writel(BM_SSP_CTRL0_XFER_COUNT,