diff mbox

spi/sun6i: Add Master Sample Data Mode for SPI

Message ID 20170213120553.6479-1-viniciusfre@gmail.com
State New, archived
Headers show

Commit Message

viniciusfre@gmail.com Feb. 13, 2017, 12:05 p.m. UTC
In order to work appropriately, some SPI chips, such as
max11043, require SPI master samples the data at the
correct edge.

This patch add Master Sample Data Mode bit in normal sample mode.

Signed-off-by: Vinicius Maciel <viniciusfre@gmail.com>
---
 drivers/spi/spi-sun6i.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Mark Brown Feb. 13, 2017, 6:34 p.m. UTC | #1
On Mon, Feb 13, 2017 at 09:05:53AM -0300, Vinicius Maciel wrote:
> In order to work appropriately, some SPI chips, such as
> max11043, require SPI master samples the data at the
> correct edge.

As I said on another version of this patch this should really be done by
implementing the SPI modes - there isn't one universal configuration for
SPI devices unfortunately.
Mark Brown Feb. 13, 2017, 7:06 p.m. UTC | #2
On Mon, Feb 13, 2017 at 04:00:09PM -0300, Vinicius Maciel wrote:
> Hi Mark,

Please don't top post, reply in line with needed context.  This allows
readers to readily follow the flow of conversation and understand what
you are talking about and also helps ensure that everything in the
discussion is being addressed.

> Sorry for the mess up. sun6i is a reference to the Allwinner A31 processor
> and sun7i is a reference to the Allwinner A20 processor. A31 uses
> spi-sun6i.c code, while A20 uses spi-sun4i.c code. Therefore, this is a
> different patch.
> About your recommedantion, I have to check with Maxine what can be done.

Usually duplicate patches to the two drivers are sent as a series to
make sure it's the same thing being done twice.
diff mbox

Patch

diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
index e3114832c485..170f4ad407dd 100644
--- a/drivers/spi/spi-sun6i.c
+++ b/drivers/spi/spi-sun6i.c
@@ -43,6 +43,7 @@ 
 #define SUN6I_TFR_CTL_CS_LEVEL			BIT(7)
 #define SUN6I_TFR_CTL_DHB			BIT(8)
 #define SUN6I_TFR_CTL_FBS			BIT(12)
+#define SUN6I_TFR_CTL_SDM			BIT(13)
 #define SUN6I_TFR_CTL_XCH			BIT(31)
 
 #define SUN6I_INT_CTL_REG		0x10
@@ -342,6 +343,8 @@  static int sun6i_spi_runtime_resume(struct device *dev)
 
 	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
 			SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
+        sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG,
+			SUN6I_TFR_CTL_SDM);
 
 	return 0;