From patchwork Sun May 21 13:09:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 9739063 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 889E460326 for ; Sun, 21 May 2017 13:09:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7899A286B7 for ; Sun, 21 May 2017 13:09:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 67B80286DC; Sun, 21 May 2017 13:09:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EC43F286DF for ; Sun, 21 May 2017 13:09:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756016AbdEUNJx (ORCPT ); Sun, 21 May 2017 09:09:53 -0400 Received: from hauke-m.de ([5.39.93.123]:36645 "EHLO mail.hauke-m.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753071AbdEUNJs (ORCPT ); Sun, 21 May 2017 09:09:48 -0400 Received: from hauke-desktop.lan (p2003008628380100610A1109F04F7762.dip0.t-ipconnect.de [IPv6:2003:86:2838:100:610a:1109:f04f:7762]) by mail.hauke-m.de (Postfix) with ESMTPSA id 176431001D9; Sun, 21 May 2017 15:09:46 +0200 (CEST) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, linux-mtd@lists.infradead.org, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, martin.blumenstingl@googlemail.com, john@phrozen.org, linux-spi@vger.kernel.org, hauke.mehrtens@intel.com, robh@kernel.org, Hauke Mehrtens Subject: [PATCH v2 06/15] Documentation: DT: MIPS: lantiq: Add docs for the RCU bindings Date: Sun, 21 May 2017 15:09:09 +0200 Message-Id: <20170521130918.27446-7-hauke@hauke-m.de> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170521130918.27446-1-hauke@hauke-m.de> References: <20170521130918.27446-1-hauke@hauke-m.de> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Martin Blumenstingl This adds the initial documentation for the RCU module (a MFD device which provides USB PHYs, reset controllers and more). The RCU register range is used for multiple purposes. Mostly one device uses one or multiple register exclusively, but for some registers some bits are for one driver and some other bits are for a different driver. With this patch all accesses to the RCU registers will go through syscon. Signed-off-by: Hauke Mehrtens --- .../devicetree/bindings/mips/lantiq/rcu.txt | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/lantiq/rcu.txt diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt new file mode 100644 index 000000000000..118d04fca582 --- /dev/null +++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt @@ -0,0 +1,84 @@ +Lantiq XWAY SoC RCU binding +=========================== + +This binding describes the RCU (reset controller unit) multifunction device, +where each sub-device has it's own set of registers. + +The RCU register range is used for multiple purposes. Mostly one device +uses one or multiple register exclusively, but for some registers some +bits are for one driver and some other bits are for a different driver. +With this patch all accesses to the RCU registers will go through +syscon. + + +------------------------------------------------------------------------------- +Required properties: +- compatible : The first and second values must be: "simple-mfd", "syscon" +- reg : The address and length of the system control registers + + +------------------------------------------------------------------------------- +Example of the RCU bindings on a xRX200 SoC: + rcu0: rcu@203000 { + compatible = "lantiq,rcu-xrx200", "simple-mfd", "syscon"; + reg = <0x203000 0x100>; + big-endian; + + gphy0: gphy@0 { + compatible = "lantiq,xrx200a2x-rcu-gphy"; + lantiq,rcu-syscon = <&rcu0 0x20>; + resets = <&reset0 31 30>; + reset-names = "gphy"; + lantiq,gphy-mode = ; + clocks = <&pmu0 XRX200_PMU_GATE_GPHY>; + clock-names = "gphy"; + }; + + gphy1: gphy@1 { + compatible = "lantiq,xrx200a2x-rcu-gphy"; + lantiq,rcu-syscon = <&rcu0 0x68>; + resets = <&reset0 29 28>; + reset-names = "gphy"; + lantiq,gphy-mode = ; + clocks = <&pmu0 XRX200_PMU_GATE_GPHY>; + clock-names = "gphy"; + }; + + reset0: reset@0 { + compatible = "lantiq,rcu-reset"; + lantiq,rcu-syscon = <&rcu0 0x10 0x14>; + #reset-cells = <2>; + }; + + reset1: reset@1 { + compatible = "lantiq,rcu-reset"; + lantiq,rcu-syscon = <&rcu0 0x48 0x24>; + #reset-cells = <2>; + }; + + usb_phy0: usb2-phy@0 { + compatible = "lantiq,xrx200-rcu-usb2-phy"; + + lantiq,rcu-syscon = <&rcu0 0x18 0x38>; + resets = <&reset1 4 4>, <&reset0 4 4>; + reset-names = "phy", "ctrl"; + #phy-cells = <0>; + }; + + usb_phy1: usb2-phy@1 { + compatible = "lantiq,xrx200-rcu-usb2-phy"; + + lantiq,rcu-syscon = <&rcu0 0x34 0x3C>; + resets = <&reset1 5 5>, <&reset0 4 4>; + reset-names = "phy", "ctrl"; + #phy-cells = <0>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&rcu0>; + offset = <0x10>; + mask = <0x40000000>; + }; + }; +