From patchwork Fri Aug 4 00:00:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 9880137 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D58A0603F4 for ; Fri, 4 Aug 2017 00:02:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C658228932 for ; Fri, 4 Aug 2017 00:02:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BB30928936; Fri, 4 Aug 2017 00:02:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A96A228932 for ; Fri, 4 Aug 2017 00:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752005AbdHDABc (ORCPT ); Thu, 3 Aug 2017 20:01:32 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:33719 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752066AbdHDAAg (ORCPT ); Thu, 3 Aug 2017 20:00:36 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 0C9AE8365B; Fri, 4 Aug 2017 12:00:34 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail; t=1501804834; bh=gN1XIccbFawvzMA423s5HgDq76PkJPAGp/J3wpA+d3s=; h=From:To:Subject:Date:In-Reply-To:References; b=zBymOyDjvdnoH4OXAbXXnQQUhdhjHoOx7TxRhDbFUI0VR48UZ4N9zAoerDQpDUphk dkU576d98Ki2i+UGVgmB0H+zPxcR053SKF0TyI60mHbXXMesjLqgqw/+jKusNCoFk7 fJyD1rPdN73nnQivMwHTZ83A0iBctHGJLjtRu4Fs= Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 04 Aug 2017 12:00:33 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.30]) by smtp (Postfix) with ESMTP id 99D1513EEEB; Fri, 4 Aug 2017 12:00:41 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id EBB0B1E1D0C; Fri, 4 Aug 2017 12:00:33 +1200 (NZST) From: Chris Packham To: broonie@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, andy.shevchenko@gmail.com, hsweeten@visionengravers.com Subject: [PATCH v2 1/7] spi: spi-ep93xx: remove io wrappers Date: Fri, 4 Aug 2017 12:00:17 +1200 Message-Id: <20170804000023.15624-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170804000023.15624-1-chris.packham@alliedtelesis.co.nz> References: <20170804000023.15624-1-chris.packham@alliedtelesis.co.nz> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: H Hartley Sweeten The io wrappers just add obfuscation to the driver. Remove them. Signed-off-by: H Hartley Sweeten --- drivers/spi/spi-ep93xx.c | 72 +++++++++++++++++------------------------------- 1 file changed, 25 insertions(+), 47 deletions(-) diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c index b5d766064b7b..49c42a6c2be1 100644 --- a/drivers/spi/spi-ep93xx.c +++ b/drivers/spi/spi-ep93xx.c @@ -72,7 +72,7 @@ * struct ep93xx_spi - EP93xx SPI controller structure * @pdev: pointer to platform device * @clk: clock for the controller - * @regs_base: pointer to ioremap()'d registers + * @mmio: pointer to ioremap()'d registers * @sspdr_phys: physical address of the SSPDR register * @wait: wait here until given transfer is completed * @current_msg: message that is currently processed (or %NULL if none) @@ -92,7 +92,7 @@ struct ep93xx_spi { const struct platform_device *pdev; struct clk *clk; - void __iomem *regs_base; + void __iomem *mmio; unsigned long sspdr_phys; struct completion wait; struct spi_message *current_msg; @@ -111,28 +111,6 @@ struct ep93xx_spi { /* converts bits per word to CR0.DSS value */ #define bits_per_word_to_dss(bpw) ((bpw) - 1) -static void ep93xx_spi_write_u8(const struct ep93xx_spi *espi, - u16 reg, u8 value) -{ - writeb(value, espi->regs_base + reg); -} - -static u8 ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg) -{ - return readb(spi->regs_base + reg); -} - -static void ep93xx_spi_write_u16(const struct ep93xx_spi *espi, - u16 reg, u16 value) -{ - writew(value, espi->regs_base + reg); -} - -static u16 ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg) -{ - return readw(spi->regs_base + reg); -} - static int ep93xx_spi_enable(const struct ep93xx_spi *espi) { u8 regval; @@ -142,9 +120,9 @@ static int ep93xx_spi_enable(const struct ep93xx_spi *espi) if (err) return err; - regval = ep93xx_spi_read_u8(espi, SSPCR1); + regval = readb(espi->mmio + SSPCR1); regval |= SSPCR1_SSE; - ep93xx_spi_write_u8(espi, SSPCR1, regval); + writeb(regval, espi->mmio + SSPCR1); return 0; } @@ -153,9 +131,9 @@ static void ep93xx_spi_disable(const struct ep93xx_spi *espi) { u8 regval; - regval = ep93xx_spi_read_u8(espi, SSPCR1); + regval = readb(espi->mmio + SSPCR1); regval &= ~SSPCR1_SSE; - ep93xx_spi_write_u8(espi, SSPCR1, regval); + writeb(regval, espi->mmio + SSPCR1); clk_disable(espi->clk); } @@ -164,18 +142,18 @@ static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi) { u8 regval; - regval = ep93xx_spi_read_u8(espi, SSPCR1); + regval = readb(espi->mmio + SSPCR1); regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); - ep93xx_spi_write_u8(espi, SSPCR1, regval); + writeb(regval, espi->mmio + SSPCR1); } static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi) { u8 regval; - regval = ep93xx_spi_read_u8(espi, SSPCR1); + regval = readb(espi->mmio + SSPCR1); regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE); - ep93xx_spi_write_u8(espi, SSPCR1, regval); + writeb(regval, espi->mmio + SSPCR1); } /** @@ -252,8 +230,8 @@ static int ep93xx_spi_chip_setup(const struct ep93xx_spi *espi, spi->mode, div_cpsr, div_scr, dss); dev_dbg(&espi->pdev->dev, "setup: cr0 %#x\n", cr0); - ep93xx_spi_write_u8(espi, SSPCPSR, div_cpsr); - ep93xx_spi_write_u16(espi, SSPCR0, cr0); + writeb(div_cpsr, espi->mmio + SSPCPSR); + writew(cr0, espi->mmio + SSPCR0); return 0; } @@ -265,14 +243,14 @@ static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t) if (t->tx_buf) tx_val = ((u16 *)t->tx_buf)[espi->tx]; - ep93xx_spi_write_u16(espi, SSPDR, tx_val); + writew(tx_val, espi->mmio + SSPDR); espi->tx += sizeof(tx_val); } else { u8 tx_val = 0; if (t->tx_buf) tx_val = ((u8 *)t->tx_buf)[espi->tx]; - ep93xx_spi_write_u8(espi, SSPDR, tx_val); + writeb(tx_val, espi->mmio + SSPDR); espi->tx += sizeof(tx_val); } } @@ -282,14 +260,14 @@ static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t) if (t->bits_per_word > 8) { u16 rx_val; - rx_val = ep93xx_spi_read_u16(espi, SSPDR); + rx_val = readw(espi->mmio + SSPDR); if (t->rx_buf) ((u16 *)t->rx_buf)[espi->rx] = rx_val; espi->rx += sizeof(rx_val); } else { u8 rx_val; - rx_val = ep93xx_spi_read_u8(espi, SSPDR); + rx_val = readb(espi->mmio + SSPDR); if (t->rx_buf) ((u8 *)t->rx_buf)[espi->rx] = rx_val; espi->rx += sizeof(rx_val); @@ -313,7 +291,7 @@ static int ep93xx_spi_read_write(struct ep93xx_spi *espi) struct spi_transfer *t = msg->state; /* read as long as RX FIFO has frames in it */ - while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) { + while ((readb(espi->mmio + SSPSR) & SSPSR_RNE)) { ep93xx_do_read(espi, t); espi->fifo_level--; } @@ -615,14 +593,14 @@ static void ep93xx_spi_process_message(struct ep93xx_spi *espi, * Just to be sure: flush any data from RX FIFO. */ timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT); - while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) { + while (readw(espi->mmio + SSPSR) & SSPSR_RNE) { if (time_after(jiffies, timeout)) { dev_warn(&espi->pdev->dev, "timeout while flushing RX FIFO\n"); msg->status = -ETIMEDOUT; return; } - ep93xx_spi_read_u16(espi, SSPDR); + readw(espi->mmio + SSPDR); } /* @@ -671,7 +649,7 @@ static int ep93xx_spi_transfer_one_message(struct spi_master *master, static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) { struct ep93xx_spi *espi = dev_id; - u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR); + u8 irq_status = readb(espi->mmio + SSPIIR); /* * If we got ROR (receive overrun) interrupt we know that something is @@ -679,7 +657,7 @@ static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id) */ if (unlikely(irq_status & SSPIIR_RORIS)) { /* clear the overrun interrupt */ - ep93xx_spi_write_u8(espi, SSPICR, 0); + writeb(0, espi->mmio + SSPICR); dev_warn(&espi->pdev->dev, "receive overrun, aborting the message\n"); espi->current_msg->status = -EIO; @@ -862,9 +840,9 @@ static int ep93xx_spi_probe(struct platform_device *pdev) espi->sspdr_phys = res->start + SSPDR; - espi->regs_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(espi->regs_base)) { - error = PTR_ERR(espi->regs_base); + espi->mmio = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(espi->mmio)) { + error = PTR_ERR(espi->mmio); goto fail_release_master; } @@ -879,7 +857,7 @@ static int ep93xx_spi_probe(struct platform_device *pdev) dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n"); /* make sure that the hardware is disabled */ - ep93xx_spi_write_u8(espi, SSPCR1, 0); + writeb(0, espi->mmio + SSPCR1); error = devm_spi_register_master(&pdev->dev, master); if (error) {