| Message ID | 20181002013142.209751-1-ryandcase@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v5,1/2] dt-bindings: spi: Qualcomm Quad SPI(QSPI) documentation | expand |
Quoting Ryan Case (2018-10-01 18:31:41) > From: Girish Mahadevan <girishm@codeaurora.org> > > Bindings for Qualcomm Quad SPI used on SoCs such as sdm845. > > Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> > Signed-off-by: Ryan Case <ryandcase@chromium.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Hi, On Mon, Oct 1, 2018 at 6:32 PM Ryan Case <ryandcase@chromium.org> wrote: > > From: Girish Mahadevan <girishm@codeaurora.org> > > Bindings for Qualcomm Quad SPI used on SoCs such as sdm845. > > Signed-off-by: Girish Mahadevan <girishm@codeaurora.org> > Signed-off-by: Ryan Case <ryandcase@chromium.org> > --- > > Changes in v5: > - None > > Changes in v4: > - Changed qspi@ to spi@ and device@ to flash@ to match Rob's review Rob said that with those changes you could add his reviewed by [1], so this patch should have carried: Reviewed-by: Rob Herring <robh@kernel.org> I'd also say that usually when changes are minor you can make a judgement call and carry previous reviews. If there's any question about whether previous reviews can be carried you can mention it somewhere in your changelog. In this particular case I would have called the changes minor / non-controversial so I would have kept Stephen and my reviews when posting the new patch. In any case Stephen has already re-provided his review and you can feel free to add: Reviewed-by: Douglas Anderson <dianders@chromium.org> [1] https://lkml.kernel.org/r/20180927204624.GA7072@bogus
On Mon, Oct 01, 2018 at 06:31:41PM -0700, Ryan Case wrote: > From: Girish Mahadevan <girishm@codeaurora.org> > > Bindings for Qualcomm Quad SPI used on SoCs such as sdm845. Please use subject lines matching the style for the subsystem. This makes it easier for people to identify relevant patches.
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt new file mode 100644 index 000000000000..1d64b61f5171 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.txt @@ -0,0 +1,36 @@ +Qualcomm Quad Serial Peripheral Interface (QSPI) + +The QSPI controller allows SPI protocol communication in single, dual, or quad +wire transmission modes for read/write access to slaves such as NOR flash. + +Required properties: +- compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as + "qcom,sdm845-qspi", "qcom,qspi-v1" +- reg: Should contain the base register location and length. +- interrupts: Interrupt number used by the controller. +- clocks: Should contain the core and AHB clock. +- clock-names: Should be "core" for core clock and "iface" for AHB clock. + +SPI slave nodes must be children of the SPI master node and can contain +properties described in Documentation/devicetree/bindings/spi/spi-bus.txt + +Example: + + qspi: spi@88df000 { + compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; + reg = <0x88df000 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "iface", "core"; + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; + };