diff mbox series

[05/11] DT: marvell,mmp2: Add SSP1 and SSP3

Message ID 20181010170936.316862-6-lkundrak@v3.sk (mailing list archive)
State New, archived
Headers show
Series spi: pxa2xx: add DT and slave mode support | expand

Commit Message

Lubomir Rintel Oct. 10, 2018, 5:09 p.m. UTC
There seem to be SSP2, SSP4 and perhaps SSP5 too, but Marvel keeps their
base addresses secret.

The SSP1 and SSP3 addresses were taken from OLPC 1.75, OpenFirmware and
kernel respectively.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

---
Changes since v1:
- Dropped the aliases

 arch/arm/boot/dts/mmp2.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

James Cameron Oct. 29, 2018, 5:35 a.m. UTC | #1
On Wed, Oct 10, 2018 at 07:09:30PM +0200, Lubomir Rintel wrote:
> There seem to be SSP2, SSP4 and perhaps SSP5 too, but Marvel keeps their
> base addresses secret.
> 
> The SSP1 and SSP3 addresses were taken from OLPC 1.75, OpenFirmware and
> kernel respectively.

Sorry for the delay.  Love your work!  From my notes, SSP2 is
0xd4036000, and SSP4 is 0xd4039000.  Can be probed by hand in
OpenFirmware or CForth once clocks are on.
Pavel Machek Nov. 4, 2018, 12:06 p.m. UTC | #2
On Wed 2018-10-10 19:09:30, Lubomir Rintel wrote:
> There seem to be SSP2, SSP4 and perhaps SSP5 too, but Marvel keeps their
> base addresses secret.
> 
> The SSP1 and SSP3 addresses were taken from OLPC 1.75, OpenFirmware and
> kernel respectively.
> 
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

Acked-by: Pavel Machek <pavel@ucw.cz>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 766bbb8495b6..c16531f4d4c7 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -239,6 +239,22 @@ 
 				resets = <&soc_clocks MMP2_CLK_RTC>;
 				status = "disabled";
 			};
+
+			ssp1: ssp@d4035000 {
+				compatible = "marvell,mmp2-ssp";
+				reg = <0xd4035000 0x1000>;
+				clocks = <&soc_clocks MMP2_CLK_SSP0>;
+				interrupts = <0>;
+				status = "disabled";
+			};
+
+			ssp3: ssp@d4037000 {
+				compatible = "marvell,mmp2-ssp";
+				reg = <0xd4037000 0x1000>;
+				clocks = <&soc_clocks MMP2_CLK_SSP2>;
+				interrupts = <20>;
+				status = "disabled";
+			};
 		};
 
 		soc_clocks: clocks{