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Wed, 24 Oct 2018 02:50:32 +0000 Received: from AM6PR04MB5016.eurprd04.prod.outlook.com ([fe80::14d:71ff:bbe0:a643]) by AM6PR04MB5016.eurprd04.prod.outlook.com ([fe80::14d:71ff:bbe0:a643%2]) with mapi id 15.20.1250.028; Wed, 24 Oct 2018 02:50:32 +0000 From: Clark Wang To: "broonie@kernel.org" CC: "linux-spi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Clark Wang Subject: [PATCH 5/5] spi: lpspi: CLK pin becomes low when CR_RST=1 Thread-Topic: [PATCH 5/5] spi: lpspi: CLK pin becomes low when CR_RST=1 Thread-Index: AQHUa0RU/fO2DSpo+kGys4cA/FBa8A== Date: Wed, 24 Oct 2018 02:50:32 +0000 Message-ID: <20181024024808.14485-5-xiaoning.wang@nxp.com> References: <20181024024808.14485-1-xiaoning.wang@nxp.com> In-Reply-To: <20181024024808.14485-1-xiaoning.wang@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SG2PR06CA0110.apcprd06.prod.outlook.com (2603:1096:1:1d::12) To AM6PR04MB5016.eurprd04.prod.outlook.com (2603:10a6:20b:9::24) authentication-results: spf=none (sender IP is ) smtp.mailfrom=xiaoning.wang@nxp.com; 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This RST may cause both CLK and CS pins go from high to low level under cs-gpio mode. Add fsl_lpspi_reset() function after one message transfer to clear all flags in use. Signed-off-by: Xiaoning Wang Reviewed-by: Fugang Duan --- drivers/spi/spi-fsl-lpspi.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index a8a6699e2741..844b713553d1 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -281,10 +281,6 @@ static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi) u32 temp; int ret; - temp = CR_RST; - writel(temp, fsl_lpspi->base + IMX7ULP_CR); - writel(0, fsl_lpspi->base + IMX7ULP_CR); - if (!fsl_lpspi->is_slave) { ret = fsl_lpspi_set_bitrate(fsl_lpspi); if (ret) @@ -375,6 +371,21 @@ static int fsl_lpspi_wait_for_completion(struct spi_controller *controller) return 0; } +static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi) +{ + u32 temp; + + /* W1C for all flags in SR */ + temp = 0x3F << 8; + writel(temp, fsl_lpspi->base + IMX7ULP_SR); + + /* Clear FIFO and disable module */ + temp = CR_RRF | CR_RTF; + writel(temp, fsl_lpspi->base + IMX7ULP_CR); + + return 0; +} + static int fsl_lpspi_transfer_one(struct spi_controller *controller, struct spi_device *spi, struct spi_transfer *t) @@ -396,9 +407,7 @@ static int fsl_lpspi_transfer_one(struct spi_controller *controller, if (ret) return ret; - ret = fsl_lpspi_txfifo_empty(fsl_lpspi); - if (ret) - return ret; + fsl_lpspi_reset(fsl_lpspi); return 0; }