Message ID | 20190110212451.12108-1-linus.walleij@linaro.org (mailing list archive) |
---|---|
State | Accepted |
Commit | 6e0a32d6f376ea22a34ae3a8df60adafbcdb0c86 |
Headers | show |
Series | [v2] spi: dw: Fix default polarity of native chipselect | expand |
Hi Linus, > On 10 Jan 2019, at 22:24, Linus Walleij <linus.walleij@linaro.org> wrote: > > Janek can you confirm if this in combination > with the previous patch solves your problem? This patch changes the behavior of the DesignWare SPI. I don’t use this IP, I can’t test this patch. The driver I had issues with was the Cadence one, spi-cadence.c. Regards, Janek
On Fri, Jan 11, 2019 at 11:27 AM Janek Kotas <jank@cadence.com> wrote: > > On 10 Jan 2019, at 22:24, Linus Walleij <linus.walleij@linaro.org> wrote: > > > > Janek can you confirm if this in combination > > with the previous patch solves your problem? > > This patch changes the behavior of the DesignWare SPI. > I don’t use this IP, I can’t test this patch. > > The driver I had issues with was the Cadence one, spi-cadence.c. Sorry for the misunderstanding! I sent a patch for the cadence driver as well, I will forward it to you if you can't find it in your inbox. Yours, Linus Walleij
Hello: The following patches were marked "accepted", because they were applied to broonie/spi.git (refs/heads/for-next): Series: [1/4,v3] spi: Support high CS when using descriptors Submitter: Linus Walleij <linus.walleij@linaro.org> Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=67187 Patches: [1/4,v3] spi: Support high CS when using descriptors [2/4,v3] spi: dw: Fix default polarity of native chipselect [3/4,v3] spi: cadence: Fix default polarity of native chipselect [4/4,v3] gpio: of: Fix logic inversion Patch: spi: Support high CS when using descriptors Submitter: Linus Walleij <linus.walleij@linaro.org> Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=64533 Patch: spi: cadence: Fix default polarity of native chipselect Submitter: Linus Walleij <linus.walleij@linaro.org> Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=64835 Patch: [v2] spi: dw: Fix default polarity of native chipselect Submitter: Linus Walleij <linus.walleij@linaro.org> Patchwork: https://patchwork.kernel.org/project/spi-devel-general/list/?series=64831 Total patches: 7
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index f54b498001a9..64164f1a83f4 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c @@ -137,11 +137,10 @@ void dw_spi_set_cs(struct spi_device *spi, bool enable) struct dw_spi *dws = spi_controller_get_devdata(spi->controller); struct chip_data *chip = spi_get_ctldata(spi); - /* Chip select logic is inverted from spi_set_cs() */ if (chip && chip->cs_control) - chip->cs_control(!enable); + chip->cs_control(enable); - if (!enable) + if (enable) dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select)); else if (dws->cs_override) dw_writel(dws, DW_SPI_SER, 0);
The DW controller also supports platforms specifying native chipselects. When I enforce the use of high CS for drivers opting in for using GPIO descriptors, I inadvertedly switched the driver to also use active high chip select for native chip selects. As it turns out, the DW hardware driving chip selects also thinks it is weird with active low chip selects so all we need to do is remove an inversion in the driver. Cc: Janek Kotas <jank@cadence.com> Reported-by: Janek Kotas <jank@cadence.com> Fixes: 9400c41e77b8 ("spi: dw: Convert to use CS GPIO descriptors") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- ChangeLog v1->v2: - Missed to alter the actually native chip select line control code. I need to be more awake. Janek can you confirm if this in combination with the previous patch solves your problem? --- drivers/spi/spi-dw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)