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Wed, 27 Mar 2019 14:30:52 +0000 Received: from AM6PR10MB2661.EURPRD10.PROD.OUTLOOK.COM ([fe80::a442:a35b:115a:ef14]) by AM6PR10MB2661.EURPRD10.PROD.OUTLOOK.COM ([fe80::a442:a35b:115a:ef14%2]) with mapi id 15.20.1750.014; Wed, 27 Mar 2019 14:30:52 +0000 From: Rasmus Villemoes To: Mark Brown , "linux-spi@vger.kernel.org" CC: "linux-kernel@vger.kernel.org" , Fabio Estevam , Rasmus Villemoes Subject: [RFC PATCH 3/4] spi: spi-fsl-spi: allow changing bits_per_word while CS is still active Thread-Topic: [RFC PATCH 3/4] spi: spi-fsl-spi: allow changing bits_per_word while CS is still active Thread-Index: AQHU5KmtcGfHbrXiqki/KvhP3QsOXw== Date: Wed, 27 Mar 2019 14:30:51 +0000 Message-ID: <20190327143040.16013-4-rasmus.villemoes@prevas.dk> References: <20190327143040.16013-1-rasmus.villemoes@prevas.dk> In-Reply-To: <20190327143040.16013-1-rasmus.villemoes@prevas.dk> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HE1PR0402CA0055.eurprd04.prod.outlook.com (2603:10a6:7:7c::44) To AM6PR10MB2661.EURPRD10.PROD.OUTLOOK.COM (2603:10a6:20b:a5::31) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Rasmus.Villemoes@prevas.se; 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received-spf: None (protection.outlook.com: prevas.se does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: DRj/FXXbVNwPurmqv8L4o8jTHpQj04EW99f38Y1NkG3a+41qfR13sbqJHndifJVUkBSkxnumXLt+he4Xk6JzW1MnvNCMel/Y1ua4IfWx0a4LgYvDngUpL825/dedsyMS4IzBSkC8aVQmzf+ulKyQ7/qIa++0hgRX92yctO1g17rKZNDvAan2FPrKMPWRRvYJgbv0KU5p4O13hSaH6SqGPEdDShfi/v8x4ZhvMiU0pxvWpZgN7KiCMum7PvlG5N7X1Mu02B9F9UXZqtZeiCrJEpnCSc71jJ2tabjDLmYEpJYdARWUmXnquQTTswOQT0gIds1E7aE4AWKjZhN8LQFn9z3VhuCrmmZEDvC1TGKhWl8lzxeRQC6T0hDc+pXXbdOyEB0/oQe86jLY8FS3nI+szHf4jczwIg3MC944yjYaEUI= MIME-Version: 1.0 X-OriginatorOrg: prevas.dk X-MS-Exchange-CrossTenant-Network-Message-Id: 81f6e81a-5bea-4d80-e6df-08d6b2c0d03c X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2019 14:30:52.0043 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d350cf71-778d-4780-88f5-071a4cb1ed61 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR10MB1877 Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Commit c9bfcb315104 (spi_mpc83xx: much improved driver) introduced logic to ensure bits_per_word and speed_hz stay the same for a series of spi_transfers with CS active, arguing that The current driver may cause glitches on SPI CLK line since one must disable the SPI controller before changing any HW settings. This sounds quite reasonable. So this is a quite naive attempt at relaxing this sanity checking to only ensure that speed_hz is constant - in the faint hope that if we do not causes changes to the clock-related fields of the SPMODE register (DIV16 and PM), those glitches won't appear. The purpose of this change is to allow automatically optimizing large transfers to use 32 bits-per-word; taking one interrupt for every byte is extremely slow. Signed-off-by: Rasmus Villemoes --- drivers/spi/spi-fsl-spi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 481b075689b5..e2b341943796 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -367,7 +367,7 @@ static int fsl_spi_do_one_msg(struct spi_master *master, struct spi_transfer *t, *first; unsigned int cs_change; const int nsecs = 50; - int status; + int status, last_bpw; /* Don't allow changes if CS is active */ cs_change = 1; @@ -375,21 +375,22 @@ static int fsl_spi_do_one_msg(struct spi_master *master, if (cs_change) first = t; cs_change = t->cs_change; - if ((first->bits_per_word != t->bits_per_word) || - (first->speed_hz != t->speed_hz)) { + if (first->speed_hz != t->speed_hz) { dev_err(&spi->dev, - "bits_per_word/speed_hz cannot change while CS is active\n"); + "speed_hz cannot change while CS is active\n"); return -EINVAL; } } + last_bpw = -1; cs_change = 1; status = -EINVAL; list_for_each_entry(t, &m->transfers, transfer_list) { - if (cs_change) + if (cs_change || last_bpw != t->bits_per_word) status = fsl_spi_setup_transfer(spi, t); if (status < 0) break; + last_bpw = t->bits_per_word; if (cs_change) { fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);