| Message ID | 20201222184425.7028-5-p.yadav@ti.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 7512eaf54190e4cc9247f18439c008d44b15022c |
| Headers | show |
| Series | spi: cadence-quadspi: Add Octal DTR support | expand |
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 6a778014ff60..376abef43530 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -294,7 +294,7 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) { unsigned int dummy_clk; - dummy_clk = op->dummy.nbytes * 8; + dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); return dummy_clk; }
SPI MEM deals with dummy bytes but the controller deals with dummy cycles. Multiplying bytes by 8 is correct if the dummy phase uses 1S mode since 1 byte will be sent in 8 cycles. But if the dummy phase uses 4S mode then 1 byte will be sent in 2 cycles. To correctly translate dummy bytes to dummy cycles, the dummy buswidth also needs to be taken into account. Divide 8 by the buswidth to get the correct multiplier for getting the number of cycles. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)