| Message ID | 20210608023305.25371-1-jon.lin@rock-chips.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add Rockchip SFC(serial flash controller) support | expand |
On 6/8/21 4:33 AM, Jon Lin wrote: > From: Chris Morgan <macromorgan@hotmail.com> > > Add a devicetree entry for the Rockchip SFC for the RK3036 SOC. > > Signed-off-by: Chris Morgan <macromorgan@hotmail.com> > Signed-off-by: Jon Lin <jon.lin@rock-chips.com> > --- > > Changes in v6: None > Changes in v5: None > Changes in v4: None > Changes in v3: None > Changes in v2: None > Changes in v1: None > > arch/arm/boot/dts/rk3036.dtsi | 42 +++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi > index e24230d50a78..e7faf815ca74 100644 > --- a/arch/arm/boot/dts/rk3036.dtsi > +++ b/arch/arm/boot/dts/rk3036.dtsi > @@ -206,6 +206,17 @@ > status = "disabled"; > }; > > + sfc: spi@10208000 { > + compatible = "rockchip,rk3036-sfc"; > + reg = <0x10208000 0x4000>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>; > + clock-names = "hclk_sfc", "clk_sfc"; > + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; > + pinctrl-names = "default"; > + status = "disabled"; > + }; > + > sdmmc: mmc@10214000 { > compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; > reg = <0x10214000 0x4000>; > @@ -684,6 +695,37 @@ > }; > }; > > + serial_flash { sfc { Nodes are sort alphabetically. Sort other patches with sfc nodes in this serie as well. Maybe rename nodename consistent with sfc label? Similar to nfc nodes? > + sfc_bus4: sfc-bus4 { > + rockchip,pins = > + <1 RK_PD0 3 &pcfg_pull_none>, > + <1 RK_PD1 3 &pcfg_pull_none>, > + <1 RK_PD2 3 &pcfg_pull_none>, > + <1 RK_PD3 3 &pcfg_pull_none>; Keep align with the rest in the pinctrl node. Check that in other sfc patches as well. > + }; > + > + sfc_bus2: sfc-bus2 { > + rockchip,pins = > + <1 RK_PD0 3 &pcfg_pull_none>, > + <1 RK_PD1 3 &pcfg_pull_none>; dito > + }; > + > + sfc_cs0: sfc-cs0 { > + rockchip,pins = > + <2 RK_PA2 3 &pcfg_pull_none>; dito > + }; > + > + sfc_cs1: sfc-cs1 { > + rockchip,pins = > + <2 RK_PA3 3 &pcfg_pull_none>; dito > + }; > + > + sfc_clk: sfc-clk { > + rockchip,pins = > + <2 RK_PA4 3 &pcfg_pull_none>; dito > + }; > + }; > + > emac { > emac_xfer: emac-xfer { > rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */ >
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index e24230d50a78..e7faf815ca74 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -206,6 +206,17 @@ status = "disabled"; }; + sfc: spi@10208000 { + compatible = "rockchip,rk3036-sfc"; + reg = <0x10208000 0x4000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>; + clock-names = "hclk_sfc", "clk_sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -684,6 +695,37 @@ }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_none>, + <1 RK_PD1 3 &pcfg_pull_none>, + <1 RK_PD2 3 &pcfg_pull_none>, + <1 RK_PD3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_none>, + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <2 RK_PA2 3 &pcfg_pull_none>; + }; + + sfc_cs1: sfc-cs1 { + rockchip,pins = + <2 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <2 RK_PA4 3 &pcfg_pull_none>; + }; + }; + emac { emac_xfer: emac-xfer { rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */