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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2021 16:38:57.8605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e0e39a6-d101-4cb3-eccd-08d93b1c646d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT044.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5185 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org -Add device ID for new generation of platform. -Modify spi_busy and opcode commands based on controller version. Reviewed-by: Shyam Sundar S K Reviewed-by: Liang Liang Signed-off-by: Nehal Bakulchandra Shah Reported-by: kernel test robot Reported-by: kernel test robot --- drivers/spi/spi-amd.c | 72 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 63 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/drivers/spi/spi-amd.c b/drivers/spi/spi-amd.c index 3cf76096a76d..e65e7178d5fe 100644 --- a/drivers/spi/spi-amd.c +++ b/drivers/spi/spi-amd.c @@ -14,10 +14,12 @@ #include #define AMD_SPI_CTRL0_REG 0x00 +#define AMD_SPI_OPCODE_REG 0x45 +#define AMD_SPI_CMD_TRIGGER_REG 0x47 #define AMD_SPI_EXEC_CMD BIT(16) #define AMD_SPI_FIFO_CLEAR BIT(20) #define AMD_SPI_BUSY BIT(31) - +#define AMD_SPI_TRIGGER_CMD BIT(7) #define AMD_SPI_OPCODE_MASK 0xFF #define AMD_SPI_ALT_CS_REG 0x1D @@ -34,11 +36,31 @@ #define AMD_SPI_XFER_TX 1 #define AMD_SPI_XFER_RX 2 +#ifdef CONFIG_ACPI +struct amd_spi_devtype_data { + u32 spi_status; + u8 version; +}; + +static const struct amd_spi_devtype_data spi_v1 = { + .spi_status = AMD_SPI_CTRL0_REG, + .version = 0, +}; + +static const struct amd_spi_devtype_data spi_v2 = { + .spi_status = AMD_SPI_STATUS_REG, + .version = 1, +}; +#endif + struct amd_spi { void __iomem *io_remap_addr; unsigned long io_base_addr; u32 rom_addr; u8 chip_select; + const struct amd_spi_devtype_data *devtype_data; + struct spi_device *spi_dev; + struct spi_master *master; }; static inline u8 amd_spi_readreg8(struct spi_master *master, int idx) @@ -98,6 +120,14 @@ static void amd_spi_select_chip(struct spi_master *master) AMD_SPI_ALT_CS_MASK); } +static void amd_spi_clear_chip(struct spi_master *master) +{ + struct amd_spi *amd_spi = spi_master_get_devdata(master); + u8 chip_select = amd_spi->chip_select; + + amd_spi_writereg8(master, AMD_SPI_ALT_CS_REG, chip_select & 0XFC); +} + static void amd_spi_clear_fifo_ptr(struct spi_master *master) { amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_FIFO_CLEAR, @@ -106,8 +136,13 @@ static void amd_spi_clear_fifo_ptr(struct spi_master *master) static void amd_spi_set_opcode(struct spi_master *master, u8 cmd_opcode) { - amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode, - AMD_SPI_OPCODE_MASK); + struct amd_spi *amd_spi = spi_master_get_devdata(master); + + if (!amd_spi->devtype_data->version) + amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, cmd_opcode, + AMD_SPI_OPCODE_MASK); + else + amd_spi_writereg8(master, AMD_SPI_OPCODE_REG, cmd_opcode); } static inline void amd_spi_set_rx_count(struct spi_master *master, @@ -126,17 +161,20 @@ static inline int amd_spi_busy_wait(struct amd_spi *amd_spi) { bool spi_busy; int timeout = 100000; + u32 status_reg = amd_spi->devtype_data->spi_status; /* poll for SPI bus to become idle */ spi_busy = (ioread32((u8 __iomem *)amd_spi->io_remap_addr + - AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; + status_reg) & AMD_SPI_BUSY) == AMD_SPI_BUSY; + while (spi_busy) { usleep_range(10, 20); if (timeout-- < 0) return -ETIMEDOUT; + /* poll for SPI bus to become idle */ spi_busy = (ioread32((u8 __iomem *)amd_spi->io_remap_addr + - AMD_SPI_CTRL0_REG) & AMD_SPI_BUSY) == AMD_SPI_BUSY; + status_reg) & AMD_SPI_BUSY) == AMD_SPI_BUSY; } return 0; @@ -146,9 +184,16 @@ static void amd_spi_execute_opcode(struct spi_master *master) { struct amd_spi *amd_spi = spi_master_get_devdata(master); + /*Check for busy wait*/ + amd_spi_busy_wait(amd_spi); + /* Set ExecuteOpCode bit in the CTRL0 register */ - amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, - AMD_SPI_EXEC_CMD); + if (!amd_spi->devtype_data->version) + amd_spi_setclear_reg32(master, AMD_SPI_CTRL0_REG, AMD_SPI_EXEC_CMD, + AMD_SPI_EXEC_CMD); + else + amd_spi_setclear_reg8(master, AMD_SPI_CMD_TRIGGER_REG, AMD_SPI_TRIGGER_CMD, + AMD_SPI_TRIGGER_CMD); amd_spi_busy_wait(amd_spi); } @@ -241,7 +286,8 @@ static int amd_spi_master_transfer(struct spi_master *master, * program the controller. */ amd_spi_fifo_xfer(amd_spi, master, msg); - + if (amd_spi->devtype_data->version) + amd_spi_clear_chip(master); return 0; } @@ -266,6 +312,11 @@ static int amd_spi_probe(struct platform_device *pdev) dev_err(dev, "error %d ioremap of SPI registers failed\n", err); goto err_free_master; } + amd_spi->devtype_data = device_get_match_data(dev); + if (!amd_spi->devtype_data) { + err = -ENODEV; + goto err_free_master; + } dev_dbg(dev, "io_remap_address: %p\n", amd_spi->io_remap_addr); /* Initialize the spi_master fields */ @@ -293,7 +344,10 @@ static int amd_spi_probe(struct platform_device *pdev) #ifdef CONFIG_ACPI static const struct acpi_device_id spi_acpi_match[] = { - { "AMDI0061", 0 }, + { "AMDI0061", + .driver_data = (kernel_ulong_t)&spi_v1 }, + { "AMDI0062", + .driver_data = (kernel_ulong_t)&spi_v2 }, {}, }; MODULE_DEVICE_TABLE(acpi, spi_acpi_match);