[1/1] spi: mediatek: fix build warnning in set cs timing

Commit Message

Mason Zhang Aug. 9, 2021, 5:59 a.m. UTC

this patch fixed the build warnning in set cs timing.

Signed-off-by: Mason Zhang <[e-mail]>
---
 drivers/spi/spi-mt65xx.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Mark Brown Aug. 9, 2021, 3:02 p.m. UTC | #1

On Mon, 9 Aug 2021 13:59:12 +0800, Mason Zhang wrote:
> this patch fixed the build warnning in set cs timing.
> 
> 
> 
> 

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/1] spi: mediatek: fix build warnning in set cs timing
      commit: 5c842e51ac63130a1344650b0a95bdc398666947

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Patch

diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index bb09592bc009..2f83599642fd 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -214,7 +214,7 @@  static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
 	struct spi_delay *cs_setup = &spi->cs_setup;
 	struct spi_delay *cs_hold = &spi->cs_hold;
 	struct spi_delay *cs_inactive = &spi->cs_inactive;
-	u16 setup, hold, inactive;
+	u32 setup, hold, inactive;
 	u32 reg_val;
 	int delay;
 
@@ -239,8 +239,8 @@  static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
 
 	reg_val = readl(mdata->base + SPI_CFG0_REG);
 	if (mdata->dev_comp->enhance_timing) {
-		hold = min(hold, 0xffff);
-		setup = min(setup, 0xffff);
+		hold = min_t(u32, hold, 0x10000);
+		setup = min_t(u32, setup, 0x10000);
 		reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
 		reg_val |= (((hold - 1) & 0xffff)
 			   << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
@@ -248,8 +248,8 @@  static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
 		reg_val |= (((setup - 1) & 0xffff)
 			   << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
 	} else {
-		hold = min(hold, 0xff);
-		setup = min(setup, 0xff);
+		hold = min_t(u32, hold, 0x100);
+		setup = min_t(u32, setup, 0x100);
 		reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
 		reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
 		reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
@@ -258,7 +258,7 @@  static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
 	}
 	writel(reg_val, mdata->base + SPI_CFG0_REG);
 
-	inactive = min(inactive, 0xff);
+	inactive = min_t(u32, inactive, 0x100);
 	reg_val = readl(mdata->base + SPI_CFG1_REG);
 	reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
 	reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);